public inbox for linux-sunxi@lists.linux.dev
 help / color / mirror / Atom feed
From: Andre Przywara <andre.przywara@arm.com>
To: Yixun Lan <dlan@gentoo.org>
Cc: u-boot@lists.denx.de, linux-sunxi@lists.linux.dev,
	Jagan Teki <jagan@amarulasolutions.com>,
	Tom Rini <trini@konsulko.com>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	Paul Kocialkowski <contact@paulk.fr>,
	Samuel Holland <samuel@sholland.org>
Subject: Re: [PATCH v3 1/9] power: regulator: add AXP318W support
Date: Tue, 20 Jan 2026 00:10:10 +0100	[thread overview]
Message-ID: <20260120001010.7b67371d@ryzen.lan> (raw)
In-Reply-To: <20260113-01-a733-soc-support-v3-1-f19dcd098f60@gentoo.org>

On Tue, 13 Jan 2026 12:01:55 +0800
Yixun Lan <dlan@gentoo.org> wrote:

Hi,

> The PMIC is also known as AXP819 in vendor pmu code
> 
> For DCDC6, 8, 9, the underlying hardware support more than two levels
> voltage step tuning, but for now only first two levels are implemented
> in this driver, hence highest voltage will be limited at seccond level.
> It actual meets board requirement in current design, and we've verified
> it in Radxa Cubie A7A board.
> 
> Following are detail explanation of voltage tuning stpes for those DCDCs:
> 
> DCDC | voltage range  | units | steps | implemented
>  6   | 0.5   -  1.2   | 10 mV | 71    | Y
>  .   | 1.22  -  1.54  | 20 mV | 17    | Y
>  .   | 1.8   -  2.4   | 20 mV | 31    | N
>  .   | 2.44  -  2.76  | 40 mV | 9     | N
>  --------------------------------------------------
>  8/9 | 0.5   -  1.2   | 10 mV | 71    | Y
>  .   | 1.22  -  1.84  | 20 mV | 32    | Y
>  .   | 1.9   -  3.4   | 100mV | 16    | N
> 
> Signed-off-by: Yixun Lan <dlan@gentoo.org>

Thanks, that looks good now:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

> ---
>  drivers/power/pmic/axp.c                |  1 +
>  drivers/power/regulator/axp_regulator.c | 50 +++++++++++++++++++++++++++++++++
>  include/axp_pmic.h                      |  1 +
>  3 files changed, 52 insertions(+)
> 
> diff --git a/drivers/power/pmic/axp.c b/drivers/power/pmic/axp.c
> index 1204ec00f8d..7d8348b0769 100644
> --- a/drivers/power/pmic/axp.c
> +++ b/drivers/power/pmic/axp.c
> @@ -95,6 +95,7 @@ static const struct udevice_id axp_pmic_ids[] = {
>  	{ .compatible = "x-powers,axp806", .data = AXP806_ID },
>  	{ .compatible = "x-powers,axp809", .data = AXP809_ID },
>  	{ .compatible = "x-powers,axp813", .data = AXP813_ID },
> +	{ .compatible = "x-powers,axp318w", .data = AXP318_ID },
>  	{ }
>  };
>  
> diff --git a/drivers/power/regulator/axp_regulator.c b/drivers/power/regulator/axp_regulator.c
> index 7794a4f5d92..16d3a8f7f90 100644
> --- a/drivers/power/regulator/axp_regulator.c
> +++ b/drivers/power/regulator/axp_regulator.c
> @@ -189,6 +189,55 @@ static const struct axp_regulator_plat axp313_regulators[] = {
>  	{ }
>  };
>  
> + /*
> +  * Only two level step tuning is implemented for DCDC6, 8, 9
> +  * so the voltage below is not support in this driver
> +  * DCDC6:   20  (v1.8 - 2.4v), 40 (2.44v - 2.76v)
> +  * DCDC8,9: 100 (1.9v - 3.4v)
> +  */
> +static const struct axp_regulator_plat axp318_regulators[] = {
> +	{  "dcdc1", 0x10, BIT(0), 0x12, 0x1f, 1000, 3400, 100, NA },
> +	{  "dcdc2", 0x10, BIT(1), 0x13, 0x7f,  500, 1540,  10, 70 },
> +	{  "dcdc3", 0x10, BIT(2), 0x14, 0x7f,  500, 1540,  10, 70 },
> +	{  "dcdc4", 0x10, BIT(3), 0x15, 0x7f,  500, 1540,  10, 70 },
> +	{  "dcdc5", 0x10, BIT(4), 0x16, 0x7f,  500, 1540,  10, 70 },
> +	{  "dcdc6", 0x10, BIT(5), 0x17, 0x7f,  500, 1540,  10, 70 },
> +	{  "dcdc7", 0x10, BIT(6), 0x18, 0x7f,  500, 1840,  10, 70 },
> +	{  "dcdc8", 0x10, BIT(7), 0x19, 0x7f,  500, 1840,  10, 70 },
> +	{  "dcdc9", 0x11, BIT(0), 0x1a, 0x7f,  500, 1840,  10, 70 },
> +	{  "aldo1", 0x20, BIT(0), 0x24, 0x1f,  500, 3400, 100, NA },
> +	{  "aldo2", 0x20, BIT(1), 0x25, 0x1f,  500, 3400, 100, NA },
> +	{  "aldo3", 0x20, BIT(2), 0x26, 0x1f,  500, 3400, 100, NA },
> +	{  "aldo4", 0x20, BIT(3), 0x27, 0x1f,  500, 3400, 100, NA },
> +	{  "aldo5", 0x20, BIT(4), 0x28, 0x1f,  500, 3400, 100, NA },
> +	{  "aldo6", 0x20, BIT(5), 0x29, 0x1f,  500, 3400, 100, NA },
> +	{  "bldo1", 0x20, BIT(6), 0x2a, 0x1f,  500, 3400, 100, NA },
> +	{  "bldo2", 0x20, BIT(7), 0x2b, 0x1f,  500, 3400, 100, NA },
> +	{  "bldo3", 0x21, BIT(0), 0x2c, 0x1f,  500, 3400, 100, NA },
> +	{  "bldo4", 0x21, BIT(1), 0x2d, 0x1f,  500, 3400, 100, NA },
> +	{  "bldo5", 0x21, BIT(2), 0x2e, 0x1f,  500, 3400, 100, NA },
> +	{  "cldo1", 0x21, BIT(3), 0x2f, 0x1f,  500, 3400, 100, NA },
> +	{  "cldo2", 0x21, BIT(4), 0x30, 0x1f,  500, 3400, 100, NA },
> +	{  "cldo3", 0x21, BIT(5), 0x31, 0x1f,  500, 3400, 100, NA },
> +	{  "cldo4", 0x21, BIT(6), 0x32, 0x1f,  500, 3400, 100, NA },
> +	{  "cldo5", 0x21, BIT(7), 0x33, 0x1f,  500, 3400, 100, NA },
> +	{  "dldo1", 0x22, BIT(0), 0x34, 0x1f,  500, 3400, 100, NA },
> +	{  "dldo2", 0x22, BIT(1), 0x35, 0x1f,  500, 3400, 100, NA },
> +	{  "dldo3", 0x22, BIT(2), 0x36, 0x1f,  500, 3400, 100, NA },
> +	{  "dldo4", 0x22, BIT(3), 0x37, 0x1f,  500, 3400, 100, NA },
> +	{  "dldo5", 0x22, BIT(4), 0x38, 0x1f,  500, 3400, 100, NA },
> +	{  "dldo6", 0x22, BIT(5), 0x39, 0x1f,  500, 3400, 100, NA },
> +	{  "eldo1", 0x22, BIT(6), 0x3a, 0x1f,  500, 1500,  25, NA },
> +	{  "eldo2", 0x22, BIT(7), 0x3b, 0x1f,  500, 1500,  25, NA },
> +	{  "eldo3", 0x23, BIT(0), 0x3c, 0x1f,  500, 1500,  25, NA },
> +	{  "eldo4", 0x23, BIT(1), 0x3d, 0x1f,  500, 1500,  25, NA },
> +	{  "eldo5", 0x23, BIT(2), 0x3e, 0x1f,  500, 1500,  25, NA },
> +	{  "eldo6", 0x23, BIT(3), 0x3f, 0x1f,  500, 1500,  25, NA },
> +	{ "swout1", 0x11, BIT(3),   NA,   NA,   NA,   NA,  NA, NA },
> +	{ "swout2", 0x11, BIT(4),   NA,   NA,   NA,   NA,  NA, NA },
> +	{ }
> +};
> +
>  /*
>   * The "dcdc2" regulator has another range, beyond 1.54V up to 3.4V, in
>   * steps of 100mV. We cannot model this easily, but also don't need that,
> @@ -318,6 +367,7 @@ static const struct axp_regulator_plat *const axp_regulators[] = {
>  	[AXP221_ID]	= axp22x_regulators,
>  	[AXP223_ID]	= axp22x_regulators,
>  	[AXP313_ID]	= axp313_regulators,
> +	[AXP318_ID]	= axp318_regulators,
>  	[AXP323_ID]	= axp313_regulators,
>  	[AXP717_ID]	= axp717_regulators,
>  	[AXP803_ID]	= axp803_regulators,
> diff --git a/include/axp_pmic.h b/include/axp_pmic.h
> index 1806a7270a0..2f547da74c2 100644
> --- a/include/axp_pmic.h
> +++ b/include/axp_pmic.h
> @@ -39,6 +39,7 @@ enum {
>  	AXP806_ID,
>  	AXP809_ID,
>  	AXP813_ID,
> +	AXP318_ID,
>  };
>  
>  int axp_set_dcdc1(unsigned int mvolt);
> 


  reply	other threads:[~2026-01-19 23:11 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-13  4:01 [PATCH v3 0/9] sunxi: Add support for A733 SoC Yixun Lan
2026-01-13  4:01 ` [PATCH v3 1/9] power: regulator: add AXP318W support Yixun Lan
2026-01-19 23:10   ` Andre Przywara [this message]
2026-01-13  4:01 ` [PATCH v3 2/9] power: regulator: enable AWP318W SPL support Yixun Lan
2026-01-19 23:09   ` Andre Przywara
2026-01-13  4:01 ` [PATCH v3 3/9] sunxi: a733: uart: setup serial console Yixun Lan
2026-01-13  4:01 ` [PATCH v3 4/9] clock: a733: implement support for mmc/uart Yixun Lan
2026-01-13  4:01 ` [PATCH v3 5/9] clock: reset: a733: add initial support Yixun Lan
2026-01-13  4:02 ` [PATCH v3 6/9] gpio: " Yixun Lan
2026-01-13  4:02 ` [PATCH v3 7/9] pinctrl: sunxi: " Yixun Lan
2026-01-13  4:02 ` [PATCH v3 8/9] sunxi: mmc: enable support for A733 Yixun Lan
2026-01-13  4:02 ` [PATCH v3 9/9] sunxi: sun60i: initial support for A733 SoC Yixun Lan

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260120001010.7b67371d@ryzen.lan \
    --to=andre.przywara@arm.com \
    --cc=contact@paulk.fr \
    --cc=dlan@gentoo.org \
    --cc=jagan@amarulasolutions.com \
    --cc=jernej.skrabec@gmail.com \
    --cc=linux-sunxi@lists.linux.dev \
    --cc=samuel@sholland.org \
    --cc=trini@konsulko.com \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox