[PATCH v3 0/9] sunxi: Add support for A733 SoC

[PATCH v3 0/9] sunxi: Add support for A733 SoC

[Yixun Lan]

Allwinner A733 SoC[1] is an octa-core Cortex-A76/A55 processor, below
list the brief features. 

- Dual-core Cortex-A76, Hexa-core Cortex-A55, RISC-V E902 core
- UP to 16GB RAM, 192K+512K SRAM
- Imagination BXM-4-64 MC1 GPU
- Optional 3 TOPS NPU
- UFS3.0 storage
- eMMC, SD, SDIO
- Octal SPI
- HDMI, RGB, LVDS, eDP, MIPI display interface
- MIPI CSI, up 4 lanes
- Audio 5x I2S
- GMAC Ethernet
- USB3.1, 2.0 support
- PCIe 3.0 DM

Add support for Allwinner A733 SoC, target to support booting mainline
U-boot via FEL download mode, also add eMMC driver support, make it
able to load images from the eMMC/SD storage device.

I've not pushed DT part patches, but put a more complete working branch
at my development branch[2] for reference or testing if people
interested. Please note, we reply on vendor boot0 firmware for the DDR
initialization, then use sunxi-fel to down and execute U-Boot, see doc[3].

Link: https://linux-sunxi.org/A733 [1]
Link: https://github.com/dlan17/u-boot/tree/allwinner/A733/next [2]
Link: https://github.com/dlan17/a733/blob/main/boot-fel.md [3]
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
Changes in v3:
- power: fix format issue, move patch to first, fix SPL config
- gpio/pinctrl: rename config to SUNXI_A733_PINCTRL
- refactor get_mclk_offset()
- Link to v2: https://lore.kernel.org/r/20251130-01-a733-soc-support-v2-0-18bdd4376fad@gentoo.org

Changes in v2:
- reuse CONFIG_SUNXI_GEN_NCAT2
- merge clock initialization code with H6 driver
- add pmu driver for SPL stage
- rework for PIO register layout, introduce PIO_OFFSET
- squash commit for changes of Kconfig
- Link to v1: https://lore.kernel.org/r/20251116-01-a733-soc-support-v1-0-fb4c8db78e75@gentoo.org

---
Yixun Lan (9):
      power: regulator: add AXP318W support
      power: regulator: enable AWP318W SPL support
      sunxi: a733: uart: setup serial console
      clock: a733: implement support for mmc/uart
      clock: reset: a733: add initial support
      gpio: a733: add initial support
      pinctrl: sunxi: a733: add initial support
      sunxi: mmc: enable support for A733
      sunxi: sun60i: initial support for A733 SoC

 arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h |  31 ++++
 arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h |  36 +++++
 arch/arm/mach-sunxi/Kconfig                       |  14 ++
 arch/arm/mach-sunxi/board.c                       |   3 +-
 arch/arm/mach-sunxi/clock_sun50i_h6.c             |  14 +-
 arch/arm/mach-sunxi/cpu_info.c                    |   2 +
 common/spl/Kconfig                                |   3 +
 drivers/clk/sunxi/Kconfig                         |  14 ++
 drivers/clk/sunxi/Makefile                        |   2 +
 drivers/clk/sunxi/clk_a733.c                      |  75 +++++++++
 drivers/clk/sunxi/clk_a733_r.c                    |  36 +++++
 drivers/clk/sunxi/clk_sunxi.c                     |  10 ++
 drivers/gpio/Kconfig                              |   7 +
 drivers/gpio/sunxi_gpio.c                         |  17 +-
 drivers/mmc/sunxi_mmc.c                           |  28 +++-
 drivers/pinctrl/sunxi/Kconfig                     |  10 ++
 drivers/pinctrl/sunxi/pinctrl-sunxi.c             |  57 ++++++-
 drivers/power/Kconfig                             |  10 ++
 drivers/power/Makefile                            |   1 +
 drivers/power/axp_spl.c                           |  20 +++
 drivers/power/pmic/axp.c                          |   1 +
 drivers/power/regulator/axp_regulator.c           |  50 ++++++
 include/axp_pmic.h                                |   1 +
 include/configs/sun60i.h                          |  11 ++
 include/dt-bindings/clock/sun60i-a733-ccu.h       | 188 ++++++++++++++++++++++
 include/dt-bindings/clock/sun60i-a733-r-ccu.h     |  34 ++++
 include/dt-bindings/reset/sun60i-a733-ccu.h       |  85 ++++++++++
 include/dt-bindings/reset/sun60i-a733-r-ccu.h     |  22 +++
 include/sunxi_gpio.h                              |  14 ++
 29 files changed, 780 insertions(+), 16 deletions(-)
---
base-commit: 23987e10905146def3ab61e55ec912c6e742efdc
change-id: 20251115-01-a733-soc-support-67b0603c980e

Best regards,
-- 
Yixun Lan <dlan@gentoo.org>

[PATCH v3 1/9] power: regulator: add AXP318W support

[Yixun Lan]

The PMIC is also known as AXP819 in vendor pmu code

For DCDC6, 8, 9, the underlying hardware support more than two levels
voltage step tuning, but for now only first two levels are implemented
in this driver, hence highest voltage will be limited at seccond level.
It actual meets board requirement in current design, and we've verified
it in Radxa Cubie A7A board.

Following are detail explanation of voltage tuning stpes for those DCDCs:

DCDC | voltage range  | units | steps | implemented
 6   | 0.5   -  1.2   | 10 mV | 71    | Y
 .   | 1.22  -  1.54  | 20 mV | 17    | Y
 .   | 1.8   -  2.4   | 20 mV | 31    | N
 .   | 2.44  -  2.76  | 40 mV | 9     | N
 --------------------------------------------------
 8/9 | 0.5   -  1.2   | 10 mV | 71    | Y
 .   | 1.22  -  1.84  | 20 mV | 32    | Y
 .   | 1.9   -  3.4   | 100mV | 16    | N

Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 drivers/power/pmic/axp.c                |  1 +
 drivers/power/regulator/axp_regulator.c | 50 +++++++++++++++++++++++++++++++++
 include/axp_pmic.h                      |  1 +
 3 files changed, 52 insertions(+)

diff --git a/drivers/power/pmic/axp.c b/drivers/power/pmic/axp.c
index 1204ec00f8d..7d8348b0769 100644
--- a/drivers/power/pmic/axp.c
+++ b/drivers/power/pmic/axp.c
@@ -95,6 +95,7 @@ static const struct udevice_id axp_pmic_ids[] = {
 	{ .compatible = "x-powers,axp806", .data = AXP806_ID },
 	{ .compatible = "x-powers,axp809", .data = AXP809_ID },
 	{ .compatible = "x-powers,axp813", .data = AXP813_ID },
+	{ .compatible = "x-powers,axp318w", .data = AXP318_ID },
 	{ }
 };
 
diff --git a/drivers/power/regulator/axp_regulator.c b/drivers/power/regulator/axp_regulator.c
index 7794a4f5d92..16d3a8f7f90 100644
--- a/drivers/power/regulator/axp_regulator.c
+++ b/drivers/power/regulator/axp_regulator.c
@@ -189,6 +189,55 @@ static const struct axp_regulator_plat axp313_regulators[] = {
 	{ }
 };
 
+ /*
+  * Only two level step tuning is implemented for DCDC6, 8, 9
+  * so the voltage below is not support in this driver
+  * DCDC6:   20  (v1.8 - 2.4v), 40 (2.44v - 2.76v)
+  * DCDC8,9: 100 (1.9v - 3.4v)
+  */
+static const struct axp_regulator_plat axp318_regulators[] = {
+	{  "dcdc1", 0x10, BIT(0), 0x12, 0x1f, 1000, 3400, 100, NA },
+	{  "dcdc2", 0x10, BIT(1), 0x13, 0x7f,  500, 1540,  10, 70 },
+	{  "dcdc3", 0x10, BIT(2), 0x14, 0x7f,  500, 1540,  10, 70 },
+	{  "dcdc4", 0x10, BIT(3), 0x15, 0x7f,  500, 1540,  10, 70 },
+	{  "dcdc5", 0x10, BIT(4), 0x16, 0x7f,  500, 1540,  10, 70 },
+	{  "dcdc6", 0x10, BIT(5), 0x17, 0x7f,  500, 1540,  10, 70 },
+	{  "dcdc7", 0x10, BIT(6), 0x18, 0x7f,  500, 1840,  10, 70 },
+	{  "dcdc8", 0x10, BIT(7), 0x19, 0x7f,  500, 1840,  10, 70 },
+	{  "dcdc9", 0x11, BIT(0), 0x1a, 0x7f,  500, 1840,  10, 70 },
+	{  "aldo1", 0x20, BIT(0), 0x24, 0x1f,  500, 3400, 100, NA },
+	{  "aldo2", 0x20, BIT(1), 0x25, 0x1f,  500, 3400, 100, NA },
+	{  "aldo3", 0x20, BIT(2), 0x26, 0x1f,  500, 3400, 100, NA },
+	{  "aldo4", 0x20, BIT(3), 0x27, 0x1f,  500, 3400, 100, NA },
+	{  "aldo5", 0x20, BIT(4), 0x28, 0x1f,  500, 3400, 100, NA },
+	{  "aldo6", 0x20, BIT(5), 0x29, 0x1f,  500, 3400, 100, NA },
+	{  "bldo1", 0x20, BIT(6), 0x2a, 0x1f,  500, 3400, 100, NA },
+	{  "bldo2", 0x20, BIT(7), 0x2b, 0x1f,  500, 3400, 100, NA },
+	{  "bldo3", 0x21, BIT(0), 0x2c, 0x1f,  500, 3400, 100, NA },
+	{  "bldo4", 0x21, BIT(1), 0x2d, 0x1f,  500, 3400, 100, NA },
+	{  "bldo5", 0x21, BIT(2), 0x2e, 0x1f,  500, 3400, 100, NA },
+	{  "cldo1", 0x21, BIT(3), 0x2f, 0x1f,  500, 3400, 100, NA },
+	{  "cldo2", 0x21, BIT(4), 0x30, 0x1f,  500, 3400, 100, NA },
+	{  "cldo3", 0x21, BIT(5), 0x31, 0x1f,  500, 3400, 100, NA },
+	{  "cldo4", 0x21, BIT(6), 0x32, 0x1f,  500, 3400, 100, NA },
+	{  "cldo5", 0x21, BIT(7), 0x33, 0x1f,  500, 3400, 100, NA },
+	{  "dldo1", 0x22, BIT(0), 0x34, 0x1f,  500, 3400, 100, NA },
+	{  "dldo2", 0x22, BIT(1), 0x35, 0x1f,  500, 3400, 100, NA },
+	{  "dldo3", 0x22, BIT(2), 0x36, 0x1f,  500, 3400, 100, NA },
+	{  "dldo4", 0x22, BIT(3), 0x37, 0x1f,  500, 3400, 100, NA },
+	{  "dldo5", 0x22, BIT(4), 0x38, 0x1f,  500, 3400, 100, NA },
+	{  "dldo6", 0x22, BIT(5), 0x39, 0x1f,  500, 3400, 100, NA },
+	{  "eldo1", 0x22, BIT(6), 0x3a, 0x1f,  500, 1500,  25, NA },
+	{  "eldo2", 0x22, BIT(7), 0x3b, 0x1f,  500, 1500,  25, NA },
+	{  "eldo3", 0x23, BIT(0), 0x3c, 0x1f,  500, 1500,  25, NA },
+	{  "eldo4", 0x23, BIT(1), 0x3d, 0x1f,  500, 1500,  25, NA },
+	{  "eldo5", 0x23, BIT(2), 0x3e, 0x1f,  500, 1500,  25, NA },
+	{  "eldo6", 0x23, BIT(3), 0x3f, 0x1f,  500, 1500,  25, NA },
+	{ "swout1", 0x11, BIT(3),   NA,   NA,   NA,   NA,  NA, NA },
+	{ "swout2", 0x11, BIT(4),   NA,   NA,   NA,   NA,  NA, NA },
+	{ }
+};
+
 /*
  * The "dcdc2" regulator has another range, beyond 1.54V up to 3.4V, in
  * steps of 100mV. We cannot model this easily, but also don't need that,
@@ -318,6 +367,7 @@ static const struct axp_regulator_plat *const axp_regulators[] = {
 	[AXP221_ID]	= axp22x_regulators,
 	[AXP223_ID]	= axp22x_regulators,
 	[AXP313_ID]	= axp313_regulators,
+	[AXP318_ID]	= axp318_regulators,
 	[AXP323_ID]	= axp313_regulators,
 	[AXP717_ID]	= axp717_regulators,
 	[AXP803_ID]	= axp803_regulators,
diff --git a/include/axp_pmic.h b/include/axp_pmic.h
index 1806a7270a0..2f547da74c2 100644
--- a/include/axp_pmic.h
+++ b/include/axp_pmic.h
@@ -39,6 +39,7 @@ enum {
 	AXP806_ID,
 	AXP809_ID,
 	AXP813_ID,
+	AXP318_ID,
 };
 
 int axp_set_dcdc1(unsigned int mvolt);

-- 
2.52.0

[PATCH v3 2/9] power: regulator: enable AWP318W SPL support

[Yixun Lan]

Add the descriptions for the DC/DC regulators of the AXP318W, and enable
it when CONFIG_AXP318W_POWER is enabled.

Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 drivers/power/Kconfig   | 10 ++++++++++
 drivers/power/Makefile  |  1 +
 drivers/power/axp_spl.c | 20 ++++++++++++++++++++
 3 files changed, 31 insertions(+)

diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index d17337c0c3f..1b06d8a66c7 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -58,6 +58,7 @@ choice
 	default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
 	default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40
 	default AXP818_POWER if MACH_SUN8I_A83T
+	default AXP318W_POWER if MACH_SUN60I_A733
 	default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_V3S
 
 config SUNXI_NO_PMIC
@@ -140,6 +141,14 @@ config AXP818_POWER
 	Say y here to enable support for the axp818 pmic found on
 	A83T dev board.
 
+config AXP318W_POWER
+	bool "axp318w pmic support"
+	select AXP_PMIC_BUS
+	select CMD_POWEROFF
+	---help---
+	Select this to enable support for the AXP318W PMIC found on some
+	A733 boards.
+
 config SY8106A_POWER
 	bool "SY8106A pmic support"
 	depends on MACH_SUNXI_H3_H5
@@ -154,6 +163,7 @@ config AXP_I2C_ADDRESS
 	depends on ARCH_SUNXI && !SUNXI_NO_PMIC
 	default 0x36 if AXP305_POWER
 	default 0x36 if AXP313_POWER
+	default 0x36 if AXP318W_POWER
 	default 0x30 if AXP152_POWER
 	default 0x34
 	---help---
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index 3363191fdc8..1a54898c874 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_AXP152_POWER)	+= axp152.o
 obj-$(CONFIG_AXP209_POWER)	+= axp209.o
 obj-$(CONFIG_AXP305_POWER)	+= axp_spl.o
 obj-$(CONFIG_AXP313_POWER)	+= axp_spl.o
+obj-$(CONFIG_AXP318W_POWER)	+= axp_spl.o
 obj-$(CONFIG_AXP717_POWER)	+= axp_spl.o
 obj-$(CONFIG_AXP809_POWER)	+= axp809.o
 obj-$(CONFIG_AXP818_POWER)	+= axp818.o
diff --git a/drivers/power/axp_spl.c b/drivers/power/axp_spl.c
index 7c51a9b3dfb..b40f13c2261 100644
--- a/drivers/power/axp_spl.c
+++ b/drivers/power/axp_spl.c
@@ -67,6 +67,26 @@ static const struct axp_reg_desc_spl axp_spl_dcdc_regulators[] = {
 #define AXP_SHUTDOWN_REG	0x1a
 #define AXP_SHUTDOWN_MASK	BIT(7)
 
+#elif defined(CONFIG_AXP318W_POWER)				/* AXP318W */
+
+static const struct axp_reg_desc_spl axp_spl_dcdc_regulators[] = {
+	{ 0x10, BIT(0), 0x12, 0x1f, 1000, 3400, 100,  0 },
+	{ 0x10, BIT(1), 0x13, 0x7f,  500, 1540,  10, 70 },
+	{ 0x10, BIT(2), 0x14, 0x7f,  500, 1540,  10, 70 },
+	{ 0x10, BIT(3), 0x15, 0x7f,  500, 1540,  10, 70 },
+	{ 0x10, BIT(4), 0x16, 0x7f,  500, 1540,  10, 70 },
+	{ 0x10, BIT(5), 0x17, 0x7f,  500, 1540,  10, 70 },
+	{ 0x10, BIT(6), 0x18, 0x7f,  500, 1840,  10, 70 },
+	{ 0x10, BIT(7), 0x19, 0x7f,  500, 1840,  10, 70 },
+	{ 0x11, BIT(0), 0x1a, 0x7f,  500, 1840,  10, 70 },
+};
+
+#define AXP_CHIP_VERSION	0
+#define AXP_CHIP_VERSION_MASK	0
+#define AXP_CHIP_ID		0
+#define AXP_SHUTDOWN_REG	0x55
+#define AXP_SHUTDOWN_MASK	BIT(7)
+
 #elif defined(CONFIG_AXP305_POWER)				/* AXP305 */
 
 static const struct axp_reg_desc_spl axp_spl_dcdc_regulators[] = {

-- 
2.52.0

[PATCH v3 3/9] sunxi: a733: uart: setup serial console

[Yixun Lan]

Setup correct UART base address for A733 SoC.

According to Allwinner's board design, A733 SoC use the UART0 port
for serial console, so config PB9-10 pins to setup pinmux.

Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 arch/arm/mach-sunxi/board.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 432b1c10f92..72c9fc413cb 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -141,7 +141,8 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_H616_GPH_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN50I_H616_GPH_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN55I_A523)
+#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN55I_A523) || \
+				defined(CONFIG_MACH_SUN60I_A733))
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), 2);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), 2);
 	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);

-- 
2.52.0

[PATCH v3 4/9] clock: a733: implement support for mmc/uart

[Yixun Lan]

Add clock initialization support to set UART/I2C/MMC clock frequency.

Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 31 +++++++++++++++++++
 arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h | 36 +++++++++++++++++++++++
 arch/arm/mach-sunxi/clock_sun50i_h6.c             | 14 ++++++---
 3 files changed, 77 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index 45fa4ab6e57..3783e5fc0e0 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -32,6 +32,25 @@
 #define CCU_H6_UART_GATE_RESET		0x90c
 #define CCU_H6_I2C_GATE_RESET		0x91c
 
+/* A733 CCU register offsets */
+#define CCU_A733_PLL6_CFG		0x0a0
+#define CCU_A733_APB_UART_CLK_CFG	0x538
+#define CCU_A733_UART_GATE_RESET	0xe00
+
+#ifdef CONFIG_MACH_SUN60I_A733				/* A733 */
+
+#define CCU_PLL6_CFG			CCU_A733_PLL6_CFG
+#define CCU_UART_CLK_CFG		CCU_A733_APB_UART_CLK_CFG
+#define CCU_UART_GATE_RESET		CCU_A733_UART_GATE_RESET
+
+#else										/* H6 */
+
+#define CCU_PLL6_CFG			CCU_H6_PLL6_CFG
+#define CCU_UART_CLK_CFG		CCU_H6_APB2_CFG
+#define CCU_UART_GATE_RESET		CCU_H6_UART_GATE_RESET
+
+#endif
+
 /* A523 CPU PLL offsets */
 #define CPC_CPUA_PLL_CTRL		0x04
 #define CPC_DSU_PLL_CTRL		0x08
@@ -65,7 +84,11 @@
 #define CCM_PLL5_CTRL_DIV2(div0)	((div0) << 1)
 
 /* pll6 bit field */
+#ifdef CONFIG_MACH_SUN60I_A733
+#define CCM_PLL6_CTRL_P0_SHIFT		20
+#else
 #define CCM_PLL6_CTRL_P0_SHIFT		16
+#endif
 #define CCM_PLL6_CTRL_P0_MASK		(0x7 << CCM_PLL6_CTRL_P0_SHIFT)
 #define CCM_PLL6_CTRL_N_SHIFT		8
 #define CCM_PLL6_CTRL_N_MASK		(0xff << CCM_PLL6_CTRL_N_SHIFT)
@@ -115,6 +138,14 @@
 #define CCM_PSI_AHB1_AHB2_DEFAULT	0x03000002	    /* 200 MHz */
 #define CCM_APB1_DEFAULT		0x03000005	    /* APB0 really */
 #define CCM_APB2_DEFAULT		0x03000005	    /* APB1 really */
+
+#elif CONFIG_MACH_SUN60I_A733				/* A733 */
+
+#define CCM_PLL6_DEFAULT		0xee126310	    /* 1200/800/480 MHz */
+#define CCM_PSI_AHB1_AHB2_DEFAULT	0x03000002	    /* 200 MHz */
+#define CCM_APB1_DEFAULT		0x03000005	    /* APB0 really */
+#define CCM_APB2_DEFAULT		0x03000005	    /* APB1 really */
+
 #endif
 
 /* apb2 bit field */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
index bcfdc0a41c5..e12a8c18c8f 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
@@ -7,6 +7,18 @@
 #ifndef _SUNXI_CPU_SUNXI_NCAT2_H
 #define _SUNXI_CPU_SUNXI_NCAT2_H
 
+#ifdef CONFIG_MACH_SUN60I_A733
+
+#define SUNXI_CCM_BASE			0x02002000
+#define SUNXI_TIMER_BASE		0x02052000
+
+#define SUNXI_TWI0_BASE			0x02510000
+#define SUNXI_TWI1_BASE			0x02511000
+#define SUNXI_TWI2_BASE			0x02512000
+#define SUNXI_TWI3_BASE			0x02513000
+
+#else
+
 #define SUNXI_CCM_BASE			0x02001000
 #define SUNXI_TIMER_BASE		0x02050000
 
@@ -15,11 +27,15 @@
 #define SUNXI_TWI2_BASE			0x02502800
 #define SUNXI_TWI3_BASE			0x02502C00
 
+#endif
+
 #define SUNXI_SRAMC_BASE		0x03000000
 /* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */
 #define SUNXI_SIDC_BASE			0x03006000
 #define SUNXI_SID_BASE			0x03006200
+#ifndef CONFIG_MACH_SUN60I_A733
 #define SUNXI_GIC400_BASE		0x03020000
+#endif
 
 #ifdef CONFIG_MACH_SUN55I_A523
 #define SUNXI_DRAM_COM_BASE		0x03120000
@@ -27,10 +43,28 @@
 #define SUNXI_DRAM_PHY0_BASE		0x03140000
 #endif
 
+#ifdef CONFIG_MACH_SUN60I_A733
+#define SUNXI_GIC600_BASE		0x03400000
+#endif
+
 #define SUNXI_MMC0_BASE			0x04020000
 #define SUNXI_MMC1_BASE			0x04021000
 #define SUNXI_MMC2_BASE			0x04022000
 
+#ifdef CONFIG_MACH_SUN60I_A733
+
+#define SUNXI_PRCM_BASE			0x07010000
+#define SUNXI_R_WDOG_BASE		0x07021000
+#define SUNXI_R_CPUCFG_BASE		0x07050000
+#define SUNXI_R_TWI_BASE		0x07083000
+#define SUNXI_RTC_BASE			0x07090000
+
+#define SUNXI_CPUCFG_BASE		0x08860000
+
+#define SUNXI_CPU_PLL_CFG_BASE		0x08870000
+
+#else /* CONFIG_MACH_SUN60I_A733 */
+
 #ifndef CONFIG_MACH_SUN55I_A523
 #define SUNXI_R_CPUCFG_BASE		0x07000400
 #endif
@@ -50,6 +84,8 @@
 
 #define SUNXI_CPU_PLL_CFG_BASE		0x08817000
 
+#endif /* !CONFIG_MACH_SUN60I_A733 */
+
 #ifndef __ASSEMBLY__
 void sunxi_board_init(void);
 void sunxi_reset(void);
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index 80004f13a1e..5ea27fc56c5 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -16,6 +16,10 @@ void clock_init_safe(void)
 	void *const ccm = (void *)SUNXI_CCM_BASE;
 	void *const prcm = (void *)SUNXI_PRCM_BASE;
 
+	/* skip clock init for A733 for now */
+	if (IS_ENABLED(CONFIG_MACH_SUN60I_A733))
+		return;
+
 	if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
 		setbits_le32(prcm + CCU_PRCM_SYS_PWROFF_GATING, 0x10);
 	if (IS_ENABLED(CONFIG_MACH_SUN55I_A523))
@@ -82,14 +86,14 @@ void clock_init_uart(void)
 	writel(APB2_CLK_SRC_OSC24M|
 	       APB2_CLK_RATE_N_1|
 	       APB2_CLK_RATE_M(1),
-	       ccm + CCU_H6_APB2_CFG);
+	       ccm + CCU_UART_CLK_CFG);
 
 	/* open the clock for uart */
-	setbits_le32(ccm + CCU_H6_UART_GATE_RESET,
+	setbits_le32(ccm + CCU_UART_GATE_RESET,
 		     1 << (CONFIG_CONS_INDEX - 1));
 
 	/* deassert uart reset */
-	setbits_le32(ccm + CCU_H6_UART_GATE_RESET,
+	setbits_le32(ccm + CCU_UART_GATE_RESET,
 		     1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1));
 }
 
@@ -236,7 +240,7 @@ int clock_twi_onoff(int port, int state)
 unsigned int clock_get_pll6(void)
 {
 	void *const ccm = (void *)SUNXI_CCM_BASE;
-	uint32_t rval = readl(ccm + CCU_H6_PLL6_CFG);
+	u32 rval = readl(ccm + CCU_PLL6_CFG);
 	int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
 	int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
 		    CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
@@ -257,6 +261,8 @@ unsigned int clock_get_pll6(void)
 	 */
 	if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 		m = 4;
+	else if (IS_ENABLED(CONFIG_MACH_SUN60I_A733))
+		m = 1;
 	else
 		m = 2;
 

-- 
2.52.0

[PATCH v3 5/9] clock: reset: a733: add initial support

[Yixun Lan]

Add the clock and reset support to A733 SoC which cover
devices of gmac, mmc, I2C, SPI, uart, usb.

Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 drivers/clk/sunxi/Kconfig                     |  14 ++
 drivers/clk/sunxi/Makefile                    |   2 +
 drivers/clk/sunxi/clk_a733.c                  |  75 ++++++++++
 drivers/clk/sunxi/clk_a733_r.c                |  36 +++++
 drivers/clk/sunxi/clk_sunxi.c                 |  10 ++
 include/dt-bindings/clock/sun60i-a733-ccu.h   | 188 ++++++++++++++++++++++++++
 include/dt-bindings/clock/sun60i-a733-r-ccu.h |  34 +++++
 include/dt-bindings/reset/sun60i-a733-ccu.h   |  85 ++++++++++++
 include/dt-bindings/reset/sun60i-a733-r-ccu.h |  22 +++
 9 files changed, 466 insertions(+)

diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index 1c1cc82719c..03133ba86df 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -143,4 +143,18 @@ config CLK_SUN55I_A523_R
 	  This enables common clock driver support for the PRCM
 	  in Allwinner A523/T527 SoCs.
 
+config CLK_SUN60I_A733
+	bool "Clock driver for Allwinner A733"
+	default MACH_SUN60I_A733
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A733 SoC.
+
+config CLK_SUN60I_A733_R
+	bool "Clock driver for Allwinner A733 generation PRCM"
+	default MACH_SUN60I_A733
+	help
+	  This enables common clock driver support for the PRCM
+	  in Allwinner A733 SoCs.
+
 endif # CLK_SUNXI
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 93b542cebcd..943e47612ce 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -27,3 +27,5 @@ obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
 obj-$(CONFIG_CLK_SUN50I_A100) += clk_a100.o
 obj-$(CONFIG_CLK_SUN55I_A523) += clk_a523.o
 obj-$(CONFIG_CLK_SUN55I_A523_R) += clk_a523_r.o
+obj-$(CONFIG_CLK_SUN60I_A733) += clk_a733.o
+obj-$(CONFIG_CLK_SUN60I_A733_R) += clk_a733_r.o
diff --git a/drivers/clk/sunxi/clk_a733.c b/drivers/clk/sunxi/clk_a733.c
new file mode 100644
index 00000000000..e83f616628a
--- /dev/null
+++ b/drivers/clk/sunxi/clk_a733.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <clk/sunxi.h>
+#include <linux/bitops.h>
+
+#include <dt-bindings/clock/sun60i-a733-ccu.h>
+#include <dt-bindings/reset/sun60i-a733-ccu.h>
+
+static struct ccu_clk_gate a733_gates[] = {
+	[CLK_PLL_PERIPH0_200M]	= GATE_DUMMY,
+	[CLK_APB1]			= GATE_DUMMY,
+	[CLK_MBUS_GMAC0]	= GATE(0x05e4, BIT(11)),
+	[CLK_BUS_MMC0]		= GATE(0x0d0c, BIT(0)),
+	[CLK_BUS_MMC1]		= GATE(0x0d1c, BIT(0)),
+	[CLK_BUS_MMC2]		= GATE(0x0d2c, BIT(0)),
+	[CLK_BUS_UART0]		= GATE(0x0e00, BIT(0)),
+	[CLK_BUS_UART1]		= GATE(0x0e04, BIT(0)),
+	[CLK_BUS_UART2]		= GATE(0x0e08, BIT(0)),
+	[CLK_BUS_UART3]		= GATE(0x0e0c, BIT(0)),
+	[CLK_BUS_UART4]		= GATE(0x0e10, BIT(0)),
+	[CLK_BUS_UART5]		= GATE(0x0e14, BIT(0)),
+	[CLK_BUS_I2C0]		= GATE(0x0e80, BIT(0)),
+	[CLK_BUS_I2C1]		= GATE(0x0e84, BIT(0)),
+	[CLK_BUS_I2C2]		= GATE(0x0e88, BIT(0)),
+	[CLK_BUS_I2C3]		= GATE(0x0e8c, BIT(0)),
+	[CLK_SPI0]			= GATE(0x0f00, BIT(31)),
+	[CLK_SPI1]			= GATE(0x0f08, BIT(31)),
+	[CLK_BUS_SPI0]		= GATE(0x0f04, BIT(0)),
+	[CLK_BUS_SPI1]		= GATE(0x0f0c, BIT(0)),
+	[CLK_GMAC0_PHY]		= GATE(0x1410, BIT(31)),
+	[CLK_BUS_GMAC0]		= GATE(0x141c, BIT(0)),
+	[CLK_USB_OHCI0]		= GATE(0x1300, BIT(31)),
+	[CLK_USB_OHCI1]		= GATE(0x1308, BIT(31)),
+	[CLK_BUS_OHCI0]		= GATE(0x1304, BIT(0)),
+	[CLK_BUS_OHCI1]		= GATE(0x130c, BIT(0)),
+	[CLK_BUS_EHCI0]		= GATE(0x1304, BIT(4)),
+	[CLK_BUS_EHCI1]		= GATE(0x130c, BIT(4)),
+	[CLK_USB_GATE0]		= GATE(0x1304, BIT(8)),
+	[CLK_USB_GATE1]		= GATE(0x130c, BIT(8)),
+};
+
+static struct ccu_reset a733_resets[] = {
+	[RST_BUS_MMC0]		= RESET(0x0d0c, BIT(16)),
+	[RST_BUS_MMC1]		= RESET(0x0d1c, BIT(16)),
+	[RST_BUS_MMC2]		= RESET(0x0d2c, BIT(16)),
+	[RST_BUS_UART0]		= RESET(0x0e00, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x0e04, BIT(16)),
+	[RST_BUS_UART2]		= RESET(0x0e08, BIT(16)),
+	[RST_BUS_UART3]		= RESET(0x0e0c, BIT(16)),
+	[RST_BUS_UART4]		= RESET(0x0e10, BIT(16)),
+	[RST_BUS_UART5]		= RESET(0x0e14, BIT(16)),
+	[RST_BUS_I2C0]		= RESET(0x0e80, BIT(16)),
+	[RST_BUS_I2C1]		= RESET(0x0e84, BIT(16)),
+	[RST_BUS_I2C2]		= RESET(0x0e8c, BIT(16)),
+	[RST_BUS_I2C3]		= RESET(0x0e10, BIT(16)),
+	[RST_BUS_SPI0]		= RESET(0x0f04, BIT(16)),
+	[RST_BUS_SPI1]		= RESET(0x0f0c, BIT(16)),
+	[RST_BUS_GMAC0]		= RESET(0x141c, BIT(16) | BIT(17)),
+	[RST_USB_PHY0]		= RESET(0x1300, BIT(30)),
+	[RST_USB_PHY1]		= RESET(0x1308, BIT(30)),
+	[RST_BUS_OHCI0]		= RESET(0x1304, BIT(16)),
+	[RST_BUS_OHCI1]		= RESET(0x130c, BIT(16)),
+	[RST_BUS_EHCI0]		= RESET(0x1304, BIT(20)),
+	[RST_BUS_EHCI1]		= RESET(0x130c, BIT(20)),
+};
+
+const struct ccu_desc a733_ccu_desc = {
+	.gates	= a733_gates,
+	.resets	= a733_resets,
+	.num_gates = ARRAY_SIZE(a733_gates),
+	.num_resets = ARRAY_SIZE(a733_resets),
+};
diff --git a/drivers/clk/sunxi/clk_a733_r.c b/drivers/clk/sunxi/clk_a733_r.c
new file mode 100644
index 00000000000..a500cd2831d
--- /dev/null
+++ b/drivers/clk/sunxi/clk_a733_r.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <clk/sunxi.h>
+#include <dt-bindings/clock/sun60i-a733-r-ccu.h>
+#include <dt-bindings/reset/sun60i-a733-r-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate a733_r_gates[] = {
+	[CLK_R_AHB]             = GATE_DUMMY,
+	[CLK_R_APB0]            = GATE_DUMMY,
+	[CLK_R_APB1]            = GATE_DUMMY,
+	[CLK_BUS_R_TWD]         = GATE(0x12c, BIT(0)),
+	[CLK_BUS_R_UART0]       = GATE(0x18c, BIT(0)),
+	[CLK_BUS_R_I2C0]        = GATE(0x19c, BIT(0)),
+	[CLK_BUS_R_I2C1]        = GATE(0x19c, BIT(1)),
+	[CLK_BUS_R_I2C2]        = GATE(0x19c, BIT(2)),
+	[CLK_BUS_R_RTC]         = GATE(0x20c, BIT(0)),
+};
+
+static struct ccu_reset a733_r_resets[] = {
+	[RST_BUS_R_TWD]         = RESET(0x12c, BIT(16)),
+	[RST_BUS_R_UART0]       = RESET(0x18c, BIT(16)),
+	[RST_BUS_R_I2C0]        = RESET(0x19c, BIT(16)),
+	[RST_BUS_R_I2C1]        = RESET(0x19c, BIT(17)),
+	[RST_BUS_R_I2C2]        = RESET(0x19c, BIT(18)),
+	[RST_BUS_R_RTC]         = RESET(0x20c, BIT(16)),
+};
+
+const struct ccu_desc a733_r_ccu_desc = {
+	.gates = a733_r_gates,
+	.resets = a733_r_resets,
+	.num_gates = ARRAY_SIZE(a733_r_gates),
+	.num_resets = ARRAY_SIZE(a733_r_resets),
+};
diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c
index 842a0541bd6..ad90a3744a2 100644
--- a/drivers/clk/sunxi/clk_sunxi.c
+++ b/drivers/clk/sunxi/clk_sunxi.c
@@ -128,6 +128,8 @@ extern const struct ccu_desc r40_ccu_desc;
 extern const struct ccu_desc v3s_ccu_desc;
 extern const struct ccu_desc a523_ccu_desc;
 extern const struct ccu_desc a523_r_ccu_desc;
+extern const struct ccu_desc a733_ccu_desc;
+extern const struct ccu_desc a733_r_ccu_desc;
 
 static const struct udevice_id sunxi_clk_ids[] = {
 #ifdef CONFIG_CLK_SUN4I_A10
@@ -233,6 +235,14 @@ static const struct udevice_id sunxi_clk_ids[] = {
 #ifdef CONFIG_CLK_SUN55I_A523_R
 	{ .compatible = "allwinner,sun55i-a523-r-ccu",
 	  .data = (ulong)&a523_r_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN60I_A733
+	{ .compatible = "allwinner,sun60i-a733-ccu",
+	  .data = (ulong)&a733_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN60I_A733_R
+	{ .compatible = "allwinner,sun60i-a733-r-ccu",
+	  .data = (ulong)&a733_r_ccu_desc },
 #endif
 	{ }
 };
diff --git a/include/dt-bindings/clock/sun60i-a733-ccu.h b/include/dt-bindings/clock/sun60i-a733-ccu.h
new file mode 100644
index 00000000000..113738ebd7e
--- /dev/null
+++ b/include/dt-bindings/clock/sun60i-a733-ccu.h
@@ -0,0 +1,188 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+
+#ifndef _DT_BINDINGS_CLK_SUN60I_A733_CCU_H_
+#define _DT_BINDINGS_CLK_SUN60I_A733_CCU_H_
+
+#define CLK_PLL_DDR0		0
+#define CLK_PLL_PERIPH0_4X	1
+#define CLK_PLL_PERIPH0_2X	2
+#define CLK_PLL_PERIPH0_800M	3
+#define CLK_PLL_PERIPH0_480M	4
+#define CLK_PLL_PERIPH0_600M	5
+#define CLK_PLL_PERIPH0_400M	6
+#define CLK_PLL_PERIPH0_300M	7
+#define CLK_PLL_PERIPH0_200M	8
+#define CLK_PLL_PERIPH0_160M	9
+#define CLK_PLL_PERIPH0_150M	10
+#define CLK_PLL_PERIPH1_4X	11
+#define CLK_PLL_PERIPH1_2X	12
+#define CLK_PLL_PERIPH1_800M	13
+#define CLK_PLL_PERIPH1_480M	14
+#define CLK_PLL_PERIPH1_600M	15
+#define CLK_PLL_PERIPH1_400M	16
+#define CLK_PLL_PERIPH1_300M	17
+#define CLK_PLL_PERIPH1_200M	18
+#define CLK_PLL_PERIPH1_160M	19
+#define CLK_PLL_PERIPH1_150M	20
+#define CLK_PLL_GPU		21
+#define CLK_PLL_VIDEO0_8X	22
+#define CLK_PLL_VIDEO0_4X	23
+#define CLK_PLL_VIDEO0_3X	24
+#define CLK_PLL_VIDEO1_8X	25
+#define CLK_PLL_VIDEO1_4X	26
+#define CLK_PLL_VIDEO1_3X	27
+#define CLK_PLL_VIDEO2_8X	28
+#define CLK_PLL_VIDEO2_4X	29
+#define CLK_PLL_VIDEO2_3X	30
+#define CLK_PLL_VIDEO3_8X	31
+#define CLK_PLL_VIDEO3_4X	32
+#define CLK_PLL_VIDEO3_3X	33
+#define CLK_PLL_VE		34
+#define CLK_PLL_AUDIO0_4X	35
+#define CLK_PLL_AUDIO0_2X	36
+#define CLK_PLL_AUDIO0		37
+#define CLK_PLL_NPU_4X		38
+#define CLK_PLL_NPU_2X		39
+#define CLK_PLL_NPU		40
+#define CLK_AHB			41
+#define CLK_APB0		42
+#define CLK_APB1		43
+#define CLK_MBUS		44
+#define CLK_DE			45
+#define CLK_BUS_DE		46
+#define CLK_DI			47
+#define CLK_BUS_DI		48
+#define CLK_G2D			49
+#define CLK_BUS_G2D		50
+#define CLK_GPU			51
+#define CLK_BUS_GPU		52
+#define CLK_CE			53
+#define CLK_BUS_CE		54
+#define CLK_BUS_CE_SYS		55
+#define CLK_VE			56
+#define CLK_BUS_VE		57
+#define CLK_BUS_DMA		58
+#define CLK_BUS_MSGBOX		59
+#define CLK_BUS_SPINLOCK	60
+#define CLK_HSTIMER0		61
+#define CLK_HSTIMER1		62
+#define CLK_HSTIMER2		63
+#define CLK_HSTIMER3		64
+#define CLK_HSTIMER4		65
+#define CLK_HSTIMER5		66
+#define CLK_BUS_HSTIMER		67
+#define CLK_BUS_DBG		68
+#define CLK_BUS_PWM0		69
+#define CLK_BUS_PWM1		70
+#define CLK_IOMMU		71
+#define CLK_BUS_IOMMU		72
+#define CLK_DRAM		73
+#define CLK_MBUS_DMA		74
+#define CLK_MBUS_VE		75
+#define CLK_MBUS_CE		76
+#define CLK_MBUS_CSI		77
+#define CLK_MBUS_ISP		78
+#define CLK_MBUS_GMAC0		79
+#define CLK_BUS_DRAM		80
+#define CLK_NAND0		81
+#define CLK_NAND1		82
+#define CLK_BUS_NAND		83
+#define CLK_MMC0		84
+#define CLK_MMC1		85
+#define CLK_MMC2		86
+#define CLK_BUS_SYSDAP		87
+#define CLK_BUS_MMC0		88
+#define CLK_BUS_MMC1		89
+#define CLK_BUS_MMC2		90
+#define CLK_BUS_UART0		91
+#define CLK_BUS_UART1		92
+#define CLK_BUS_UART2		93
+#define CLK_BUS_UART3		94
+#define CLK_BUS_UART4		95
+#define CLK_BUS_UART5		96
+#define CLK_BUS_UART6		97
+#define CLK_BUS_UART7		98
+#define CLK_BUS_I2C0		99
+#define CLK_BUS_I2C1		100
+#define CLK_BUS_I2C2		101
+#define CLK_BUS_I2C3		102
+#define CLK_BUS_I2C4		103
+#define CLK_BUS_I2C5		104
+#define CLK_BUS_CAN		105
+#define CLK_SPI0		106
+#define CLK_SPI1		107
+#define CLK_SPI2		108
+#define CLK_SPIFC		109
+#define CLK_BUS_SPI0		110
+#define CLK_BUS_SPI1		111
+#define CLK_BUS_SPI2		112
+#define CLK_BUS_SPIFC		113
+#define CLK_GMAC0_PHY		114
+#define CLK_EMAC1_25M		115
+#define CLK_BUS_GMAC0		116
+#define CLK_BUS_GMAC1		117
+#define CLK_IR_RX		118
+#define CLK_BUS_IR_RX		119
+#define CLK_IR_TX		120
+#define CLK_BUS_IR_TX		121
+#define CLK_GPADC0		122
+#define CLK_GPADC1		123
+#define CLK_BUS_GPADC0		124
+#define CLK_BUS_GPADC1		125
+#define CLK_BUS_THS		126
+#define CLK_USB_OHCI0		127
+#define CLK_USB_OHCI1		128
+#define CLK_BUS_OHCI0		129
+#define CLK_BUS_OHCI1		130
+#define CLK_BUS_EHCI0		131
+#define CLK_BUS_EHCI1		132
+#define CLK_BUS_OTG		133
+#define CLK_BUS_LRADC		134
+#define CLK_PCIE_AUX		135
+#define CLK_BUS_DISPLAY0_TOP	136
+#define CLK_BUS_DISPLAY1_TOP	137
+#define CLK_HDMI_24M		138
+#define CLK_HDMI_CEC_32K	139
+#define CLK_HDMI_CEC		140
+#define CLK_BUS_HDMI		141
+#define CLK_MIPI_DSI0		142
+#define CLK_MIPI_DSI1		143
+#define CLK_BUS_MIPI_DSI0	144
+#define CLK_BUS_MIPI_DSI1	145
+#define CLK_TCON_LCD0		146
+#define CLK_TCON_LCD1		147
+#define CLK_TCON_LCD2		148
+#define CLK_COMBOPHY_DSI0	149
+#define CLK_COMBOPHY_DSI1	150
+#define CLK_BUS_TCON_LCD0	151
+#define CLK_BUS_TCON_LCD1	152
+#define CLK_BUS_TCON_LCD2	153
+#define CLK_TCON_TV0		154
+#define CLK_TCON_TV1		155
+#define CLK_BUS_TCON_TV0	156
+#define CLK_BUS_TCON_TV1	157
+#define CLK_EDP			158
+#define CLK_BUS_EDP		159
+#define CLK_LEDC		160
+#define CLK_BUS_LEDC		161
+#define CLK_CSI_TOP		162
+#define CLK_CSI_MCLK0		163
+#define CLK_CSI_MCLK1		164
+#define CLK_CSI_MCLK2		165
+#define CLK_CSI_MCLK3		166
+#define CLK_BUS_CSI		167
+#define CLK_ISP			168
+#define CLK_DSP			169
+#define CLK_FANOUT_24M		170
+#define CLK_FANOUT_12M		171
+#define CLK_FANOUT_16M		172
+#define CLK_FANOUT_25M		173
+#define CLK_FANOUT_27M		174
+#define CLK_FANOUT_PCLK		175
+#define CLK_FANOUT0		176
+#define CLK_FANOUT1		177
+#define CLK_FANOUT2		178
+#define CLK_USB_GATE0		179
+#define CLK_USB_GATE1		180
+
+#endif /* _DT_BINDINGS_CLK_SUN60I_A733_CCU_H_ */
diff --git a/include/dt-bindings/clock/sun60i-a733-r-ccu.h b/include/dt-bindings/clock/sun60i-a733-r-ccu.h
new file mode 100644
index 00000000000..e16ee48968d
--- /dev/null
+++ b/include/dt-bindings/clock/sun60i-a733-r-ccu.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+
+#ifndef _DT_BINDINGS_CLK_SUN60I_A733_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN60I_A733_R_CCU_H_
+
+#define CLK_R_AHB		0
+#define CLK_R_APB0		1
+#define CLK_R_APB1		2
+#define CLK_R_TIMER0		3
+#define CLK_R_TIMER1		4
+#define CLK_R_TIMER2		5
+#define CLK_BUS_R_TIMER		6
+#define CLK_BUS_R_TWD		7
+#define CLK_R_PWMCTRL		8
+#define CLK_BUS_R_PWMCTRL	9
+#define CLK_R_SPI		10
+#define CLK_BUS_R_SPI		11
+#define CLK_BUS_R_SPINLOCK	12
+#define CLK_BUS_R_MSGBOX	13
+#define CLK_BUS_R_UART0		14
+#define CLK_BUS_R_UART1		15
+#define CLK_BUS_R_I2C0		16
+#define CLK_BUS_R_I2C1		17
+#define CLK_BUS_R_I2C2		18
+#define CLK_BUS_R_PPU0		19
+#define CLK_BUS_R_PPU1		20
+#define CLK_BUS_R_CPU_BIST	21
+#define CLK_R_IR_RX		22
+#define CLK_BUS_R_IR_RX		23
+#define CLK_BUS_R_DMA		24
+#define CLK_BUS_R_RTC		25
+#define CLK_BUS_R_CPUCFG	26
+
+#endif /* _DT_BINDINGS_CLK_SUN60I_A733_R_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun60i-a733-ccu.h b/include/dt-bindings/reset/sun60i-a733-ccu.h
new file mode 100644
index 00000000000..ed81633c80b
--- /dev/null
+++ b/include/dt-bindings/reset/sun60i-a733-ccu.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+
+#ifndef _DT_BINDINGS_RST_SUN60I_A733_CCU_H_
+#define _DT_BINDINGS_RST_SUN60I_A733_CCU_H_
+
+#define RST_MBUS		0
+#define RST_BUS_NSI		1
+#define RST_BUS_DE		2
+#define RST_BUS_DI		3
+#define RST_BUS_G2D		4
+#define RST_BUS_SYS		5
+#define RST_BUS_GPU		6
+#define RST_BUS_CE		7
+#define RST_BUS_SYS_CE		8
+#define RST_BUS_VE		9
+#define RST_BUS_DMA		10
+#define RST_BUS_MSGBOX		11
+#define RST_BUS_SPINLOCK	12
+#define RST_BUS_CPUXTIMER	13
+#define RST_BUS_DBG		14
+#define RST_BUS_PWM0		15
+#define RST_BUS_PWM1		16
+#define RST_BUS_DRAM		17
+#define RST_BUS_NAND		18
+#define RST_BUS_MMC0		19
+#define RST_BUS_MMC1		20
+#define RST_BUS_MMC2		21
+#define RST_BUS_SYSDAP		22
+#define RST_BUS_UART0		23
+#define RST_BUS_UART1		24
+#define RST_BUS_UART2		25
+#define RST_BUS_UART3		26
+#define RST_BUS_UART4		27
+#define RST_BUS_UART5		28
+#define RST_BUS_UART6		29
+#define RST_BUS_UART7		30
+#define RST_BUS_I2C0		31
+#define RST_BUS_I2C1		32
+#define RST_BUS_I2C2		33
+#define RST_BUS_I2C3		34
+#define RST_BUS_I2C4		35
+#define RST_BUS_I2C5		36
+#define RST_BUS_CAN		37
+#define RST_BUS_SPI0		38
+#define RST_BUS_SPI1		39
+#define RST_BUS_SPI2		40
+#define RST_BUS_SPIFC		41
+#define RST_BUS_GMAC0		42
+#define RST_BUS_GMAC1		43
+#define RST_BUS_IR_RX		44
+#define RST_BUS_IR_TX		45
+#define RST_BUS_GPADC0		46
+#define RST_BUS_GPADC1		47
+#define RST_BUS_THS		48
+#define RST_USB_PHY0		49
+#define RST_USB_PHY1		50
+#define RST_BUS_OHCI0		51
+#define RST_BUS_OHCI1		52
+#define RST_BUS_EHCI0		53
+#define RST_BUS_EHCI1		54
+#define RST_BUS_OTG		55
+#define RST_BUS_3		56
+#define RST_BUS_LRADC		57
+#define RST_BUS_PCIE_USB3	58
+#define RST_BUS_DISPLAY0_TOP	59
+#define RST_BUS_DISPLAY1_TOP	60
+#define RST_BUS_HDMI_MAIN	61
+#define RST_BUS_HDMI_SUB	62
+#define RST_BUS_MIPI_DSI0	63
+#define RST_BUS_MIPI_DSI1	64
+#define RST_BUS_TCON_LCD0	65
+#define RST_BUS_TCON_LCD1	66
+#define RST_BUS_TCON_LCD2	67
+#define RST_BUS_TCON_TV0	68
+#define RST_BUS_TCON_TV1	69
+#define RST_BUS_LVDS0		70
+#define RST_BUS_LVDS1		71
+#define RST_BUS_EDP		72
+#define RST_BUS_VIDEO_OUT0	73
+#define RST_BUS_VIDEO_OUT1	74
+#define RST_BUS_LEDC		75
+#define RST_BUS_CSI		76
+#define RST_BUS_ISP		77
+
+#endif /* _DT_BINDINGS_RST_SUN60I_A733_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun60i-a733-r-ccu.h b/include/dt-bindings/reset/sun60i-a733-r-ccu.h
new file mode 100644
index 00000000000..fbf48f883b7
--- /dev/null
+++ b/include/dt-bindings/reset/sun60i-a733-r-ccu.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+
+#ifndef _DT_BINDINGS_RST_SUN60I_A733_R_CCU_H_
+#define _DT_BINDINGS_RST_SUN60I_A733_R_CCU_H_
+
+#define RST_BUS_R_TIMER		0
+#define RST_BUS_R_TWD		1
+#define RST_BUS_R_PWMCTRL	2
+#define RST_BUS_R_SPI		3
+#define RST_BUS_R_SPINLOCK	4
+#define RST_BUS_R_MSGBOX	5
+#define RST_BUS_R_UART0		6
+#define RST_BUS_R_UART1		7
+#define RST_BUS_R_I2C0		8
+#define RST_BUS_R_I2C1		9
+#define RST_BUS_R_I2C2		10
+#define RST_BUS_R_PPU1		11
+#define RST_BUS_R_IR_RX		12
+#define RST_BUS_R_RTC		13
+#define RST_BUS_R_CPUCFG	14
+
+#endif /* _DT_BINDINGS_RST_SUN60I_A733_R_CCU_H_ */

-- 
2.52.0

[PATCH v3 6/9] gpio: a733: add initial support

[Yixun Lan]

In A733 SoC, the GPIO IP block has changed its arrangement, so initial
GPIO base address and bank size need to be adjusted.

Introduce new SUNXI_NEW2_PINCTRL in order to reuse the driver in future.

There is no PA bank exist in A733, but introducing a virtual one as offset
0x80, and with the bank size 0x80, it will iterate other bank correctly
starting from PB as offset 0x100.

Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 drivers/gpio/Kconfig      |  7 +++++++
 drivers/gpio/sunxi_gpio.c | 17 ++++++++++++++---
 include/sunxi_gpio.h      | 14 ++++++++++++++
 3 files changed, 35 insertions(+), 3 deletions(-)

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index db077e472a8..7851f0e25e0 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -426,6 +426,13 @@ config SUNXI_NEW_PINCTRL
 	The Allwinner D1 and other new SoCs use a different register map
 	for the GPIO block, which we need to know about in the SPL.
 
+config SUNXI_A733_PINCTRL
+	bool
+	depends on SUNXI_GPIO
+	---help---
+	The Allwinner A733 SoCs use a different register map
+	for the GPIO block, which we need to know about in the SPL.
+
 config XILINX_GPIO
 	bool "Xilinx GPIO driver"
 	depends on DM_GPIO
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 094c45a6927..e41aa3be5d3 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -38,18 +38,26 @@
 
 #define GPIO_DAT_REG_OFFSET	0x10
 
-#define GPIO_DRV_REG_OFFSET	0x14
 
 /*		Newer SoCs use a slightly different register layout */
 #ifdef CONFIG_SUNXI_NEW_PINCTRL
 /* pin drive strength: 4 bits per pin */
+#define GPIO_DRV_REG_OFFSET	0x14
 #define GPIO_DRV_INDEX(pin)	((pin) / 8)
 #define GPIO_DRV_OFFSET(pin)	(((pin) % 8) * 4)
 
 #define GPIO_PULL_REG_OFFSET	0x24
 
+#elif CONFIG_SUNXI_A733_PINCTRL
+#define GPIO_DRV_REG_OFFSET	0x20
+#define GPIO_DRV_INDEX(pin)	((pin) / 8)
+#define GPIO_DRV_OFFSET(pin)	(((pin) % 8) * 4)
+
+#define GPIO_PULL_REG_OFFSET	0x30
+
 #else /* older generation pin controllers */
 /* pin drive strength: 2 bits per pin */
+#define GPIO_DRV_REG_OFFSET	0x14
 #define GPIO_DRV_INDEX(pin)	((pin) / 16)
 #define GPIO_DRV_OFFSET(pin)	(((pin) % 16) * 2)
 
@@ -62,15 +70,18 @@
 static void* BANK_TO_GPIO(int bank)
 {
 	void *pio_base;
+	u32 bank_size;
 
 	if (bank < SUNXI_GPIO_L) {
-		pio_base = (void *)(uintptr_t)SUNXI_PIO_BASE;
+		pio_base = (void *)(uintptr_t)(SUNXI_PIO_BASE + SUNXI_PIO_OFFSET);
+		bank_size = SUNXI_PINCTRL_BANK_SIZE;
 	} else {
 		pio_base = (void *)(uintptr_t)SUNXI_R_PIO_BASE;
+		bank_size = SUNXI_R_PINCTRL_BANK_SIZE;
 		bank -= SUNXI_GPIO_L;
 	}
 
-	return pio_base + bank * SUNXI_PINCTRL_BANK_SIZE;
+	return pio_base + bank * bank_size;
 }
 
 void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val)
diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
index 12b54c8dda4..80161fe61db 100644
--- a/include/sunxi_gpio.h
+++ b/include/sunxi_gpio.h
@@ -19,6 +19,9 @@
 #elif defined(CONFIG_SUN50I_GEN_H6)
 #define SUNXI_PIO_BASE		0x0300b000
 #define SUNXI_R_PIO_BASE	0x07022000
+#elif defined(CONFIG_MACH_SUN60I_A733)
+#define SUNXI_PIO_BASE		0x02000000
+#define SUNXI_R_PIO_BASE	0x07025000
 #elif defined(CONFIG_SUNXI_GEN_NCAT2)
 #define SUNXI_PIO_BASE		0x02000000
 #define SUNXI_R_PIO_BASE	0x07022000
@@ -172,11 +175,22 @@ enum sunxi_gpio_number {
 #ifdef CONFIG_SUNXI_NEW_PINCTRL
 	#define SUNXI_PINCTRL_BANK_SIZE	0x30
 	#define SUNXI_GPIO_DISABLE	0xf
+#elif CONFIG_SUNXI_A733_PINCTRL
+	#define SUNXI_PINCTRL_BANK_SIZE	0x80
+	#define SUNXI_GPIO_DISABLE	0xf
 #else
 	#define SUNXI_PINCTRL_BANK_SIZE	0x24
 	#define SUNXI_GPIO_DISABLE	0x7
 #endif
 
+#if CONFIG_SUNXI_A733_PINCTRL
+#define SUNXI_PIO_OFFSET		0x80 /* offset for virtual PA port */
+#define SUNXI_R_PINCTRL_BANK_SIZE	0x30
+#else
+#define SUNXI_PIO_OFFSET		0x00
+#define SUNXI_R_PINCTRL_BANK_SIZE	SUNXI_PINCTRL_BANK_SIZE
+#endif
+
 /* GPIO pin pull-up/down config */
 #define SUNXI_GPIO_PULL_DISABLE	0
 #define SUNXI_GPIO_PULL_UP	1

-- 
2.52.0

[PATCH v3 7/9] pinctrl: sunxi: a733: add initial support

[Yixun Lan]

Introduce pinctrl driver for A733 SoC, but only limited devices are
supported which includes GMAC, MMC, SPI, UART.

Setup an offset 0x80 for virtual PA port, as A733 changes the register
layout, with this adjustment, all other ports can be found correctly.

Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 drivers/pinctrl/sunxi/Kconfig         | 10 ++++++
 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 57 ++++++++++++++++++++++++++++++++++-
 2 files changed, 66 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 54314992299..0e48a71e8b5 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -149,4 +149,14 @@ config PINCTRL_SUN55I_A523_R
 	default MACH_SUN55I_A523
 	select PINCTRL_SUNXI
 
+config PINCTRL_SUN60I_A733
+	bool "Support for the Allwinner A733 PIO"
+	default MACH_SUN60I_A733
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN60I_A733_R
+	bool "Support for the Allwinner A733 R-PIO"
+	default MACH_SUN60I_A733
+	select PINCTRL_SUNXI
+
 endif
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index fd357ab0d4e..b6c901f14c1 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -30,6 +30,7 @@ struct sunxi_pinctrl_function {
 
 struct sunxi_pinctrl_desc {
 	const struct sunxi_pinctrl_function	*functions;
+	u32					pio_offset;
 	u8					num_functions;
 	u8					first_bank;
 	u8					num_banks;
@@ -195,7 +196,7 @@ static int sunxi_pinctrl_bind(struct udevice *dev)
 		return -EINVAL;
 	dev_set_priv(dev, desc);
 
-	plat->base = dev_read_addr_ptr(dev);
+	plat->base = dev_read_addr_ptr(dev) + desc->pio_offset;
 
 	ret = device_bind_driver_to_node(dev, "gpio_sunxi", dev->name,
 					 dev_ofnode(dev), &gpio_dev);
@@ -782,6 +783,32 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun55i_a523_pinctrl_desc =
 	.num_banks	= 11,
 };
 
+static const struct sunxi_pinctrl_function sun60i_a733_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+	{ "gmac0",	5 },	/* PH0-PH15 */
+	{ "gmac1",	5 },	/* PJ0-PJ15 */
+	{ "mmc0",	2 },	/* PF0-PF5 */
+	{ "mmc1",	2 },	/* PG0-PG5 */
+	{ "mmc2",	3 },	/* PC0, PC1, PC5, PC6, PC8-PC11, PC13-PC16 */
+	{ "mmc3",	4 },	/* PC0, PC1, PC5, PC6, PC8-PC11, PC13-PC16 */
+	{ "spi0",	5 },	/* PC2-PC4, PC7, PC12 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	3 },	/* PF2, PF4 */
+#else
+	{ "uart0",	2 },	/* PB9, PB10 */
+#endif
+	{ "uart1",	2 },	/* PG6, PG7 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun60i_a733_pinctrl_desc = {
+	.functions	= sun60i_a733_pinctrl_functions,
+	.pio_offset	= SUNXI_PIO_OFFSET,
+	.num_functions	= ARRAY_SIZE(sun60i_a733_pinctrl_functions),
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 11,
+};
+
 static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
@@ -847,6 +874,21 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun55i_a523_r_pinctrl_desc
 	.num_banks	= 2,
 };
 
+static const struct sunxi_pinctrl_function sun60i_a733_r_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+	{ "r_i2c0",	2 },	/* PL0-PL1 */
+	{ "r_uart0",	3 },	/* PL2-PL3 */
+	{ "r_uart1",	2 },	/* PL2-PL3 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun60i_a733_r_pinctrl_desc = {
+	.functions	= sun60i_a733_r_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun60i_a733_r_pinctrl_functions),
+	.first_bank	= SUNXI_GPIO_L,
+	.num_banks	= 2,
+};
+
 static const struct udevice_id sunxi_pinctrl_ids[] = {
 #ifdef CONFIG_PINCTRL_SUNIV_F1C100S
 	{
@@ -1034,6 +1076,19 @@ static const struct udevice_id sunxi_pinctrl_ids[] = {
 		.data = (ulong)&sun55i_a523_r_pinctrl_desc,
 	},
 #endif
+
+#ifdef CONFIG_PINCTRL_SUN60I_A733
+	{
+		.compatible = "allwinner,sun60i-a733-pinctrl",
+		.data = (ulong)&sun60i_a733_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN60I_A733_R
+	{
+		.compatible = "allwinner,sun60i-a733-r-pinctrl",
+		.data = (ulong)&sun60i_a733_r_pinctrl_desc,
+	},
+#endif
 	{}
 };
 

-- 
2.52.0

[PATCH v3 8/9] sunxi: mmc: enable support for A733

[Yixun Lan]

Minor clock adjustment for new A733 MMC controller, the SMHC0_CLK_REG
start at offset 0x400, and with step size of 0x10.

Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 drivers/mmc/sunxi_mmc.c | 28 +++++++++++++++++++++-------
 1 file changed, 21 insertions(+), 7 deletions(-)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index e28c81afffe..d7dbe1c27ed 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -112,6 +112,9 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 			if (priv->mmc_no == 2)
 				pll_hz *= 2;
 		}
+
+		if (IS_ENABLED(CONFIG_MACH_SUN60I_A733))
+			pll_hz /= 3;
 	}
 
 	div = pll_hz / hz;
@@ -167,7 +170,8 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 	}
 
 	/* The A523 has a second divider, not a shift. */
-	if (IS_ENABLED(CONFIG_MACH_SUN55I_A523))
+	if (IS_ENABLED(CONFIG_MACH_SUN55I_A523) ||
+	    IS_ENABLED(CONFIG_MACH_SUN60I_A733))
 		n = (1U << n) - 1;
 
 	writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
@@ -661,15 +665,25 @@ static const struct dm_mmc_ops sunxi_mmc_ops = {
 	.get_cd		= sunxi_mmc_getcd,
 };
 
-static unsigned get_mclk_offset(void)
+static unsigned int get_mclk_offset(int mmc_no)
 {
+	unsigned int size, offset;
+
 	if (IS_ENABLED(CONFIG_MACH_SUN9I_A80))
-		return 0x410;
+		offset = 0x410;
+	else if (IS_ENABLED(CONFIG_MACH_SUN60I_A733))
+		offset = 0xd00;
+	else if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
+		offset = 0x830;
+	else
+		offset = 0x88;
 
-	if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
-		return 0x830;
+	if (IS_ENABLED(CONFIG_MACH_SUN60I_A733))
+		size = 0x10;
+	else
+		size = 0x4;
 
-	return 0x88;
+	return offset + size * mmc_no;
 };
 
 static int sunxi_mmc_probe(struct udevice *dev)
@@ -707,7 +721,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
 	ccu_reg = (u32 *)(uintptr_t)ofnode_get_addr(args.node);
 
 	priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
-	priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * 4;
+	priv->mclkreg = (void *)ccu_reg + get_mclk_offset(priv->mmc_no);
 
 	ret = clk_get_by_name(dev, "ahb", &gate_clk);
 	if (!ret)

-- 
2.52.0

[PATCH v3 9/9] sunxi: sun60i: initial support for A733 SoC

[Yixun Lan]

Add basic support for Allwinner A733 SoC, includes SPL settings.

- Include some basic register definitions
- Introduce a new SUN60I A733 Kconfig option
- Ssetup RVBAR register properly according to docs
- Config max DDR size 16GB
- Config SRAM 0x62000 for TF-A
- Set SPL MAX SIZE to 180KB, 0x47000 - 0x74000
- Set SPL running address to 0x47000, with a header padded before
  the image, so the final SPL text address need to shift 0x60 bytes.
- Set Stack address

Signed-off-by: Yixun Lan <dlan@gentoo.org>

---
Note, Address for TF-A can be altered to other value, for example,
moving it to the DDR address space. The only requirement is that
load and run address should be matched.
---
 arch/arm/mach-sunxi/Kconfig    | 14 ++++++++++++++
 arch/arm/mach-sunxi/cpu_info.c |  2 ++
 common/spl/Kconfig             |  3 +++
 include/configs/sun60i.h       | 11 +++++++++++
 4 files changed, 30 insertions(+)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index e979ee4a2cc..b7ac828e16d 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -215,6 +215,7 @@ config SUNXI_SRAM_ADDRESS
 	hex
 	default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
 	default 0x44000 if MACH_SUN55I_A523
+	default 0x47000 if MACH_SUN60I_A733
 	default 0x20000 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2
 	default 0x0
 	---help---
@@ -228,6 +229,7 @@ config SUNXI_RVBAR_ADDRESS
 	depends on ARM64
 	default 0x08100040 if MACH_SUN50I_A133
 	default 0x08000040 if MACH_SUN55I_A523
+	default 0x08001004 if MACH_SUN60I_A733
 	default 0x09010040 if SUN50I_GEN_H6
 	default 0x017000a0
 	---help---
@@ -257,6 +259,7 @@ config SUNXI_BL31_BASE
 	default 0x40000000 if MACH_SUN50I_H616
 	default 0x00104000 if SUN50I_GEN_H6
 	default 0x00054000 if MACH_SUN55I_A523
+	default 0x00062000 if MACH_SUN60I_A733
 	default 0x0
 	help
 	  Address where BL31 (TF-A) is loaded, or zero if BL31 is not used.
@@ -339,6 +342,7 @@ config MACH_SUNXI_H3_H5
 config SUNXI_DRAM_MAX_SIZE
 	hex
 	default 0x100000000 if MACH_SUN50I_H616 || MACH_SUN50I_A133 || MACH_SUN55I_A523
+	default 0x400000000 if MACH_SUN60I_A733
 	default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
 	default 0x80000000
 
@@ -553,6 +557,15 @@ config MACH_SUN55I_A523
 	select SPL_LOAD_FIT if SPL
 	imply OF_UPSTREAM
 
+config MACH_SUN60I_A733
+	bool "sun60i (Allwinner A733)"
+	select ARM64
+	select SUNXI_GEN_NCAT2
+	select SUNXI_A733_PINCTRL
+	select FIT
+	select SPL_LOAD_FIT if SPL
+	select SUPPORT_SPL
+
 endchoice
 
 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
@@ -870,6 +883,7 @@ config SYS_CONFIG_NAME
 	default "sun50i" if MACH_SUN50I_H616
 	default "sun50i" if MACH_SUN50I_A133
 	default "sun55i" if MACH_SUN55I_A523
+	default "sun60i" if MACH_SUN60I_A733
 
 config SYS_BOARD
 	default "sunxi"
diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index c3a51d9956e..f0b33bb9097 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -108,6 +108,8 @@ int print_cpuinfo(void)
 	puts("CPU:   Allwinner A133 (SUN50I)\n");
 #elif defined CONFIG_MACH_SUN55I_A523
 	puts("CPU:   Allwinner A523 (SUN55I)\n");
+#elif defined CONFIG_MACH_SUN60I_A733
+	puts("CPU:   Allwinner A733 (SUN60I)\n");
 #else
 #warning Please update cpu_info.c with correct CPU information
 	puts("CPU:   SUNXI Family\n");
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 24d6ce5d739..ba98b76bbc6 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -81,6 +81,7 @@ config SPL_MAX_SIZE
 	default 0xec00 if OMAP34XX
 	default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB
 	default 0xbfa0 if MACH_SUN50I_H616 || MACH_SUN50I_A133 || MACH_SUN55I_A523
+	default 0x2d000 if MACH_SUN60I_A733
 	default 0x7000 if RCAR_GEN3
 	default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0
 	default 0x7fa0 if ARCH_SUNXI
@@ -279,6 +280,7 @@ config SPL_TEXT_BASE
 	default 0x40301350 if OMAP54XX
 	default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
 	default 0x44060 if MACH_SUN55I_A523
+	default 0x47060 if MACH_SUN60I_A733
 	default 0x20060 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2
 	default 0x00060 if ARCH_SUNXI
 	default 0xfffc0000 if ARCH_ZYNQMP
@@ -434,6 +436,7 @@ config SPL_STACK
 	default 0x52a00 if MACH_SUN50I_H616
 	default 0x40000 if MACH_SUN8I_R528 || MACH_SUN50I_A133
 	default 0x44000 if MACH_SUN55I_A523
+	default 0x5A000 if MACH_SUN60I_A733
 	default 0x54000 if MACH_SUN50I || MACH_SUN50I_H5
 	default 0x18000 if MACH_SUN9I
 	default 0x8000 if ARCH_SUNXI
diff --git a/include/configs/sun60i.h b/include/configs/sun60i.h
new file mode 100644
index 00000000000..70649366c1c
--- /dev/null
+++ b/include/configs/sun60i.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Placeholder wrapper to allow addressing Allwinner devices with Cortex-A55
+ * cores separately. Please do not add anything in here.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */

-- 
2.52.0

Re: [PATCH v3 2/9] power: regulator: enable AWP318W SPL support

[Andre Przywara]

On Tue, 13 Jan 2026 12:01:56 +0800
Yixun Lan <dlan@gentoo.org> wrote:

Hi,

> Add the descriptions for the DC/DC regulators of the AXP318W, and enable
> it when CONFIG_AXP318W_POWER is enabled.
> 
> Signed-off-by: Yixun Lan <dlan@gentoo.org>
> ---
>  drivers/power/Kconfig   | 10 ++++++++++
>  drivers/power/Makefile  |  1 +
>  drivers/power/axp_spl.c | 20 ++++++++++++++++++++
>  3 files changed, 31 insertions(+)
> 
> diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
> index d17337c0c3f..1b06d8a66c7 100644
> --- a/drivers/power/Kconfig
> +++ b/drivers/power/Kconfig
> @@ -58,6 +58,7 @@ choice
>  	default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
>  	default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40
>  	default AXP818_POWER if MACH_SUN8I_A83T
> +	default AXP318W_POWER if MACH_SUN60I_A733
>  	default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_V3S
>  
>  config SUNXI_NO_PMIC
> @@ -140,6 +141,14 @@ config AXP818_POWER
>  	Say y here to enable support for the axp818 pmic found on
>  	A83T dev board.
>  
> +config AXP318W_POWER
> +	bool "axp318w pmic support"
> +	select AXP_PMIC_BUS
> +	select CMD_POWEROFF
> +	---help---
> +	Select this to enable support for the AXP318W PMIC found on some
> +	A733 boards.
> +
>  config SY8106A_POWER
>  	bool "SY8106A pmic support"
>  	depends on MACH_SUNXI_H3_H5
> @@ -154,6 +163,7 @@ config AXP_I2C_ADDRESS
>  	depends on ARCH_SUNXI && !SUNXI_NO_PMIC
>  	default 0x36 if AXP305_POWER
>  	default 0x36 if AXP313_POWER
> +	default 0x36 if AXP318W_POWER
>  	default 0x30 if AXP152_POWER
>  	default 0x34
>  	---help---
> diff --git a/drivers/power/Makefile b/drivers/power/Makefile
> index 3363191fdc8..1a54898c874 100644
> --- a/drivers/power/Makefile
> +++ b/drivers/power/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_AXP152_POWER)	+= axp152.o
>  obj-$(CONFIG_AXP209_POWER)	+= axp209.o
>  obj-$(CONFIG_AXP305_POWER)	+= axp_spl.o
>  obj-$(CONFIG_AXP313_POWER)	+= axp_spl.o
> +obj-$(CONFIG_AXP318W_POWER)	+= axp_spl.o
>  obj-$(CONFIG_AXP717_POWER)	+= axp_spl.o
>  obj-$(CONFIG_AXP809_POWER)	+= axp809.o
>  obj-$(CONFIG_AXP818_POWER)	+= axp818.o
> diff --git a/drivers/power/axp_spl.c b/drivers/power/axp_spl.c
> index 7c51a9b3dfb..b40f13c2261 100644
> --- a/drivers/power/axp_spl.c
> +++ b/drivers/power/axp_spl.c
> @@ -67,6 +67,26 @@ static const struct axp_reg_desc_spl axp_spl_dcdc_regulators[] = {
>  #define AXP_SHUTDOWN_REG	0x1a
>  #define AXP_SHUTDOWN_MASK	BIT(7)
>  
> +#elif defined(CONFIG_AXP318W_POWER)				/* AXP318W */
> +
> +static const struct axp_reg_desc_spl axp_spl_dcdc_regulators[] = {
> +	{ 0x10, BIT(0), 0x12, 0x1f, 1000, 3400, 100,  0 },

That should be same "NA" symbol as the last entry, but I can fix this
up while committing.

The rest looks fine, so with that fixed, and for the records (and
patchworks):

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> +	{ 0x10, BIT(1), 0x13, 0x7f,  500, 1540,  10, 70 },
> +	{ 0x10, BIT(2), 0x14, 0x7f,  500, 1540,  10, 70 },
> +	{ 0x10, BIT(3), 0x15, 0x7f,  500, 1540,  10, 70 },
> +	{ 0x10, BIT(4), 0x16, 0x7f,  500, 1540,  10, 70 },
> +	{ 0x10, BIT(5), 0x17, 0x7f,  500, 1540,  10, 70 },
> +	{ 0x10, BIT(6), 0x18, 0x7f,  500, 1840,  10, 70 },
> +	{ 0x10, BIT(7), 0x19, 0x7f,  500, 1840,  10, 70 },
> +	{ 0x11, BIT(0), 0x1a, 0x7f,  500, 1840,  10, 70 },
> +};
> +
> +#define AXP_CHIP_VERSION	0
> +#define AXP_CHIP_VERSION_MASK	0
> +#define AXP_CHIP_ID		0
> +#define AXP_SHUTDOWN_REG	0x55
> +#define AXP_SHUTDOWN_MASK	BIT(7)
> +
>  #elif defined(CONFIG_AXP305_POWER)				/* AXP305 */
>  
>  static const struct axp_reg_desc_spl axp_spl_dcdc_regulators[] = {
> 

Re: [PATCH v3 1/9] power: regulator: add AXP318W support

[Andre Przywara]

On Tue, 13 Jan 2026 12:01:55 +0800
Yixun Lan <dlan@gentoo.org> wrote:

Hi,

> The PMIC is also known as AXP819 in vendor pmu code
> 
> For DCDC6, 8, 9, the underlying hardware support more than two levels
> voltage step tuning, but for now only first two levels are implemented
> in this driver, hence highest voltage will be limited at seccond level.
> It actual meets board requirement in current design, and we've verified
> it in Radxa Cubie A7A board.
> 
> Following are detail explanation of voltage tuning stpes for those DCDCs:
> 
> DCDC | voltage range  | units | steps | implemented
>  6   | 0.5   -  1.2   | 10 mV | 71    | Y
>  .   | 1.22  -  1.54  | 20 mV | 17    | Y
>  .   | 1.8   -  2.4   | 20 mV | 31    | N
>  .   | 2.44  -  2.76  | 40 mV | 9     | N
>  --------------------------------------------------
>  8/9 | 0.5   -  1.2   | 10 mV | 71    | Y
>  .   | 1.22  -  1.84  | 20 mV | 32    | Y
>  .   | 1.9   -  3.4   | 100mV | 16    | N
> 
> Signed-off-by: Yixun Lan <dlan@gentoo.org>

Thanks, that looks good now:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

> ---
>  drivers/power/pmic/axp.c                |  1 +
>  drivers/power/regulator/axp_regulator.c | 50 +++++++++++++++++++++++++++++++++
>  include/axp_pmic.h                      |  1 +
>  3 files changed, 52 insertions(+)
> 
> diff --git a/drivers/power/pmic/axp.c b/drivers/power/pmic/axp.c
> index 1204ec00f8d..7d8348b0769 100644
> --- a/drivers/power/pmic/axp.c
> +++ b/drivers/power/pmic/axp.c
> @@ -95,6 +95,7 @@ static const struct udevice_id axp_pmic_ids[] = {
>  	{ .compatible = "x-powers,axp806", .data = AXP806_ID },
>  	{ .compatible = "x-powers,axp809", .data = AXP809_ID },
>  	{ .compatible = "x-powers,axp813", .data = AXP813_ID },
> +	{ .compatible = "x-powers,axp318w", .data = AXP318_ID },
>  	{ }
>  };
>  
> diff --git a/drivers/power/regulator/axp_regulator.c b/drivers/power/regulator/axp_regulator.c
> index 7794a4f5d92..16d3a8f7f90 100644
> --- a/drivers/power/regulator/axp_regulator.c
> +++ b/drivers/power/regulator/axp_regulator.c
> @@ -189,6 +189,55 @@ static const struct axp_regulator_plat axp313_regulators[] = {
>  	{ }
>  };
>  
> + /*
> +  * Only two level step tuning is implemented for DCDC6, 8, 9
> +  * so the voltage below is not support in this driver
> +  * DCDC6:   20  (v1.8 - 2.4v), 40 (2.44v - 2.76v)
> +  * DCDC8,9: 100 (1.9v - 3.4v)
> +  */
> +static const struct axp_regulator_plat axp318_regulators[] = {
> +	{  "dcdc1", 0x10, BIT(0), 0x12, 0x1f, 1000, 3400, 100, NA },
> +	{  "dcdc2", 0x10, BIT(1), 0x13, 0x7f,  500, 1540,  10, 70 },
> +	{  "dcdc3", 0x10, BIT(2), 0x14, 0x7f,  500, 1540,  10, 70 },
> +	{  "dcdc4", 0x10, BIT(3), 0x15, 0x7f,  500, 1540,  10, 70 },
> +	{  "dcdc5", 0x10, BIT(4), 0x16, 0x7f,  500, 1540,  10, 70 },
> +	{  "dcdc6", 0x10, BIT(5), 0x17, 0x7f,  500, 1540,  10, 70 },
> +	{  "dcdc7", 0x10, BIT(6), 0x18, 0x7f,  500, 1840,  10, 70 },
> +	{  "dcdc8", 0x10, BIT(7), 0x19, 0x7f,  500, 1840,  10, 70 },
> +	{  "dcdc9", 0x11, BIT(0), 0x1a, 0x7f,  500, 1840,  10, 70 },
> +	{  "aldo1", 0x20, BIT(0), 0x24, 0x1f,  500, 3400, 100, NA },
> +	{  "aldo2", 0x20, BIT(1), 0x25, 0x1f,  500, 3400, 100, NA },
> +	{  "aldo3", 0x20, BIT(2), 0x26, 0x1f,  500, 3400, 100, NA },
> +	{  "aldo4", 0x20, BIT(3), 0x27, 0x1f,  500, 3400, 100, NA },
> +	{  "aldo5", 0x20, BIT(4), 0x28, 0x1f,  500, 3400, 100, NA },
> +	{  "aldo6", 0x20, BIT(5), 0x29, 0x1f,  500, 3400, 100, NA },
> +	{  "bldo1", 0x20, BIT(6), 0x2a, 0x1f,  500, 3400, 100, NA },
> +	{  "bldo2", 0x20, BIT(7), 0x2b, 0x1f,  500, 3400, 100, NA },
> +	{  "bldo3", 0x21, BIT(0), 0x2c, 0x1f,  500, 3400, 100, NA },
> +	{  "bldo4", 0x21, BIT(1), 0x2d, 0x1f,  500, 3400, 100, NA },
> +	{  "bldo5", 0x21, BIT(2), 0x2e, 0x1f,  500, 3400, 100, NA },
> +	{  "cldo1", 0x21, BIT(3), 0x2f, 0x1f,  500, 3400, 100, NA },
> +	{  "cldo2", 0x21, BIT(4), 0x30, 0x1f,  500, 3400, 100, NA },
> +	{  "cldo3", 0x21, BIT(5), 0x31, 0x1f,  500, 3400, 100, NA },
> +	{  "cldo4", 0x21, BIT(6), 0x32, 0x1f,  500, 3400, 100, NA },
> +	{  "cldo5", 0x21, BIT(7), 0x33, 0x1f,  500, 3400, 100, NA },
> +	{  "dldo1", 0x22, BIT(0), 0x34, 0x1f,  500, 3400, 100, NA },
> +	{  "dldo2", 0x22, BIT(1), 0x35, 0x1f,  500, 3400, 100, NA },
> +	{  "dldo3", 0x22, BIT(2), 0x36, 0x1f,  500, 3400, 100, NA },
> +	{  "dldo4", 0x22, BIT(3), 0x37, 0x1f,  500, 3400, 100, NA },
> +	{  "dldo5", 0x22, BIT(4), 0x38, 0x1f,  500, 3400, 100, NA },
> +	{  "dldo6", 0x22, BIT(5), 0x39, 0x1f,  500, 3400, 100, NA },
> +	{  "eldo1", 0x22, BIT(6), 0x3a, 0x1f,  500, 1500,  25, NA },
> +	{  "eldo2", 0x22, BIT(7), 0x3b, 0x1f,  500, 1500,  25, NA },
> +	{  "eldo3", 0x23, BIT(0), 0x3c, 0x1f,  500, 1500,  25, NA },
> +	{  "eldo4", 0x23, BIT(1), 0x3d, 0x1f,  500, 1500,  25, NA },
> +	{  "eldo5", 0x23, BIT(2), 0x3e, 0x1f,  500, 1500,  25, NA },
> +	{  "eldo6", 0x23, BIT(3), 0x3f, 0x1f,  500, 1500,  25, NA },
> +	{ "swout1", 0x11, BIT(3),   NA,   NA,   NA,   NA,  NA, NA },
> +	{ "swout2", 0x11, BIT(4),   NA,   NA,   NA,   NA,  NA, NA },
> +	{ }
> +};
> +
>  /*
>   * The "dcdc2" regulator has another range, beyond 1.54V up to 3.4V, in
>   * steps of 100mV. We cannot model this easily, but also don't need that,
> @@ -318,6 +367,7 @@ static const struct axp_regulator_plat *const axp_regulators[] = {
>  	[AXP221_ID]	= axp22x_regulators,
>  	[AXP223_ID]	= axp22x_regulators,
>  	[AXP313_ID]	= axp313_regulators,
> +	[AXP318_ID]	= axp318_regulators,
>  	[AXP323_ID]	= axp313_regulators,
>  	[AXP717_ID]	= axp717_regulators,
>  	[AXP803_ID]	= axp803_regulators,
> diff --git a/include/axp_pmic.h b/include/axp_pmic.h
> index 1806a7270a0..2f547da74c2 100644
> --- a/include/axp_pmic.h
> +++ b/include/axp_pmic.h
> @@ -39,6 +39,7 @@ enum {
>  	AXP806_ID,
>  	AXP809_ID,
>  	AXP813_ID,
> +	AXP318_ID,
>  };
>  
>  int axp_set_dcdc1(unsigned int mvolt);
>