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X-CSE-ConnectionGUID: hw7PG1ZVQYmfxlgIAX9W+w== X-CSE-MsgGUID: KPvYmjGySEylFK/Pbya4uQ== X-IronPort-AV: E=McAfee;i="6800,10657,11680"; a="70621901" X-IronPort-AV: E=Sophos;i="6.21,248,1763452800"; d="scan'208";a="70621901" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jan 2026 11:57:25 -0800 X-CSE-ConnectionGUID: eDHf0z5qT4K4NYlUNgWJEA== X-CSE-MsgGUID: hEhj3cZ7RfOGQf1SGFtXBw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,248,1763452800"; d="scan'208";a="244728318" Received: from lkp-server01.sh.intel.com (HELO 765f4a05e27f) ([10.239.97.150]) by orviesa001.jf.intel.com with ESMTP; 23 Jan 2026 11:57:20 -0800 Received: from kbuild by 765f4a05e27f with local (Exim 4.98.2) (envelope-from ) id 1vjNHS-00000000UP4-1mM9; Fri, 23 Jan 2026 19:57:18 +0000 Date: Sat, 24 Jan 2026 03:56:21 +0800 From: kernel test robot To: Richard Genoud , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel Cc: oe-kbuild-all@lists.linux.dev, Paul Kocialkowski , Thomas Petazzoni , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: Re: [PATCH v3 2/4] pwm: sun50i: Add H616 PWM support Message-ID: <202601240328.Lv73l3dC-lkp@intel.com> References: <20260123093322.1327389-3-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260123093322.1327389-3-richard.genoud@bootlin.com> Hi Richard, kernel test robot noticed the following build warnings: [auto build test WARNING on 9ace4753a5202b02191d54e9fdf7f9e3d02b85eb] url: https://github.com/intel-lab-lkp/linux/commits/Richard-Genoud/dt-bindings-pwm-allwinner-add-h616-pwm-compatible/20260123-174342 base: 9ace4753a5202b02191d54e9fdf7f9e3d02b85eb patch link: https://lore.kernel.org/r/20260123093322.1327389-3-richard.genoud%40bootlin.com patch subject: [PATCH v3 2/4] pwm: sun50i: Add H616 PWM support config: arc-allyesconfig (https://download.01.org/0day-ci/archive/20260124/202601240328.Lv73l3dC-lkp@intel.com/config) compiler: arc-linux-gcc (GCC) 15.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260124/202601240328.Lv73l3dC-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202601240328.Lv73l3dC-lkp@intel.com/ All warnings (new ones prefixed by >>): drivers/pwm/pwm-sun50i-h616.c: In function 'h616_add_composite_clk': >> drivers/pwm/pwm-sun50i-h616.c:720:28: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 720 | mux->reg = (u64)mux->reg + reg; | ^ drivers/pwm/pwm-sun50i-h616.c:730:29: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 730 | gate->reg = (u64)gate->reg + reg; | ^ drivers/pwm/pwm-sun50i-h616.c:740:29: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 740 | rate->reg = (u64)rate->reg + reg; | ^ vim +720 drivers/pwm/pwm-sun50i-h616.c 704 705 static int h616_add_composite_clk(struct clk_pwm_data *data, 706 void __iomem *reg, spinlock_t *lock, 707 struct device *dev, struct clk_hw **hw) 708 { 709 const struct clk_ops *mux_ops = NULL, *gate_ops = NULL, *rate_ops = NULL; 710 struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *rate_hw = NULL; 711 struct device_node *node = dev->of_node; 712 713 if (data->mux_hw) { 714 struct clk_mux *mux; 715 716 mux_hw = data->mux_hw; 717 mux = to_clk_mux(mux_hw); 718 mux->lock = lock; 719 mux_ops = mux_hw->init->ops; > 720 mux->reg = (u64)mux->reg + reg; 721 } 722 723 if (data->gate_hw) { 724 struct clk_gate *gate; 725 726 gate_hw = data->gate_hw; 727 gate = to_clk_gate(gate_hw); 728 gate->lock = lock; 729 gate_ops = gate_hw->init->ops; 730 gate->reg = (u64)gate->reg + reg; 731 } 732 733 if (data->rate_hw) { 734 struct clk_divider *rate; 735 736 rate_hw = data->rate_hw; 737 rate = to_clk_divider(rate_hw); 738 rate_ops = rate_hw->init->ops; 739 rate->lock = lock; 740 rate->reg = (u64)rate->reg + reg; 741 742 if (rate->table) { 743 const struct clk_div_table *clkt; 744 int table_size = 0; 745 746 for (clkt = rate->table; clkt->div; clkt++) 747 table_size++; 748 rate->width = order_base_2(table_size); 749 } 750 } 751 752 /* 753 * Retrieve the parent clock names from DTS for pwm-clk-srcxy 754 */ 755 if (!data->parent_names) { 756 data->num_parents = of_clk_get_parent_count(node); 757 if (data->num_parents == 0) 758 return -ENOENT; 759 760 data->parent_names = devm_kzalloc(dev, 761 sizeof(*data->parent_names), 762 GFP_KERNEL); 763 for (unsigned int i = 0; i < data->num_parents; i++) 764 data->parent_names[i] = of_clk_get_parent_name(node, i); 765 } 766 767 *hw = clk_hw_register_composite(dev, data->name, data->parent_names, 768 data->num_parents, mux_hw, 769 mux_ops, rate_hw, rate_ops, 770 gate_hw, gate_ops, data->flags); 771 772 return PTR_ERR_OR_ZERO(*hw); 773 } 774 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki