[PATCH] cedrus: Convert bitfield macros to FIELD_PREP for clarity

Andrew Geyko
2026-01-29T16:43:54Z

Use FIELD_PREP macros for VE_DEC_H265_TRIGGER and scaling list registers
to improve readability and maintain kernel style for bitfields.

Signed-off-by: Andrew Geyko <ageyko0@gmail.com>
---
.../staging/media/sunxi/cedrus/cedrus_regs.h | 28 ++++++++++---------
1 file changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
index 05e6cbc54..e8449859d 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
@@ -344,8 +344,8 @@

#define VE_DEC_H265_SCALING_LIST_CTRL0_FLAG_ENABLED BIT(31)

-#define VE_DEC_H265_SCALING_LIST_CTRL0_SRAM (0 << 30)
-#define VE_DEC_H265_SCALING_LIST_CTRL0_DEFAULT (1 << 30)
+#define VE_DEC_H265_SCALING_LIST_CTRL0_SRAM FIELD_PREP(BIT(30), 0)
+#define VE_DEC_H265_SCALING_LIST_CTRL0_DEFAULT FIELD_PREP(BIT(30), 1)

#define VE_DEC_H265_DEC_SLICE_HDR_INFO0 (VE_ENGINE_DEC_H265 + 0x20)

@@ -424,17 +424,19 @@
#define VE_DEC_H265_TRIGGER (VE_ENGINE_DEC_H265 + 0x34)

#define VE_DEC_H265_TRIGGER_TYPE_N_BITS(x) (((x) & 0x3f) << 8)
-#define VE_DEC_H265_TRIGGER_STCD_VC1 (0x02 << 4)
-#define VE_DEC_H265_TRIGGER_STCD_AVS (0x01 << 4)
-#define VE_DEC_H265_TRIGGER_STCD_HEVC (0x00 << 4)
-#define VE_DEC_H265_TRIGGER_DEC_SLICE (0x08 << 0)
-#define VE_DEC_H265_TRIGGER_INIT_SWDEC (0x07 << 0)
-#define VE_DEC_H265_TRIGGER_BYTE_ALIGN (0x06 << 0)
-#define VE_DEC_H265_TRIGGER_GET_VLCUE (0x05 << 0)
-#define VE_DEC_H265_TRIGGER_GET_VLCSE (0x04 << 0)
-#define VE_DEC_H265_TRIGGER_FLUSH_BITS (0x03 << 0)
-#define VE_DEC_H265_TRIGGER_GET_BITS (0x02 << 0)
-#define VE_DEC_H265_TRIGGER_SHOW_BITS (0x01 << 0)
+#define VE_DEC_H265_TRIGGER_STCD_MASK GENMASK(5, 4)
+#define VE_DEC_H265_TRIGGER_CMD_MASK GENMASK(3, 0)
+#define VE_DEC_H265_TRIGGER_STCD_HEVC FIELD_PREP(VE_DEC_H265_TRIGGER_STCD_MASK, 0x0)
+#define VE_DEC_H265_TRIGGER_STCD_AVS FIELD_PREP(VE_DEC_H265_TRIGGER_STCD_MASK, 0x1)
+#define VE_DEC_H265_TRIGGER_STCD_VC1 FIELD_PREP(VE_DEC_H265_TRIGGER_STCD_MASK, 0x2)
+#define VE_DEC_H265_TRIGGER_SHOW_BITS FIELD_PREP(VE_DEC_H265_TRIGGER_CMD_MASK, 0x1)
+#define VE_DEC_H265_TRIGGER_GET_BITS FIELD_PREP(VE_DEC_H265_TRIGGER_CMD_MASK, 0x2)
+#define VE_DEC_H265_TRIGGER_FLUSH_BITS FIELD_PREP(VE_DEC_H265_TRIGGER_CMD_MASK, 0x3)
+#define VE_DEC_H265_TRIGGER_GET_VLCSE FIELD_PREP(VE_DEC_H265_TRIGGER_CMD_MASK, 0x4)
+#define VE_DEC_H265_TRIGGER_GET_VLCUE FIELD_PREP(VE_DEC_H265_TRIGGER_CMD_MASK, 0x5)
+#define VE_DEC_H265_TRIGGER_BYTE_ALIGN FIELD_PREP(VE_DEC_H265_TRIGGER_CMD_MASK, 0x6)
+#define VE_DEC_H265_TRIGGER_INIT_SWDEC FIELD_PREP(VE_DEC_H265_TRIGGER_CMD_MASK, 0x7)
+#define VE_DEC_H265_TRIGGER_DEC_SLICE FIELD_PREP(VE_DEC_H265_TRIGGER_CMD_MASK, 0x8)

#define VE_DEC_H265_STATUS (VE_ENGINE_DEC_H265 + 0x38)

--
2.52.0