Re: [PATCH] arm64: dts: allwinner: Cubie A5E: enable SPI flash

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Missing `spi-rx-bus-width` and `spi-tx-bus-width` properties restrict the SPI flash to 1-bit mode despite hardware Quad SPI configuration.
- [Low] Unnecessary `#address-cells` and `#size-cells` defined in the `flash@0` node without child nodes.
--

commit 90d57abd1dc9fc1a77a15be6ce437a4b3378df17
Author: Andre Przywara <andre.przywara@arm.com>

arm64: dts: allwinner: Cubie A5E: enable SPI flash

This commit enables the SPI0 device tree node for the Cubie A5E board.
It describes the configuration for the 16MiB SPI NOR flash connected
to the SPI0 bus.

> diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
> --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
> @@ -344,6 +344,21 @@ &r_pio {
>  	vcc-pm-supply = <&reg_aldo3>;
>  };
>  
> +&spi0  {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi0_pc_pins>, <&spi0_cs0_pc_pin>,
> +		    <&spi0_hold_pc_pin>, <&spi0_wp_pc_pin>;
> +	status = "okay";
> +
> +	flash@0 {
> +		compatible = "winbond,w25q128", "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <40000000>;

Since the pinctrl-0 configuration explicitly maps the hardware WP and HOLD
pins to the SPI controller, should this node also include
spi-rx-bus-width = <4> and spi-tx-bus-width = <4>?

Without these properties, the SPI driver defaults to standard 1-bit mode,
failing to utilize the board's wired Quad SPI capabilities. Additionally,
if the board lacks external pull-ups, could muxing the active-low WP and
HOLD pins to the SPI controller in 1-bit mode leave the pins floating and
risk unintended write-protect or hold states?

> +		#address-cells = <1>;
> +		#size-cells = <1>;

This isn't a bug, but since this flash node does not contain any child
partition nodes, these #address-cells and #size-cells properties are
unnecessary and trigger standard dtc warnings.

> +	};
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260511221741.25888-1-andre.przywara@arm.com?part=1