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[9.244.8.156]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-6650163752bsm1836441d50.16.2026.06.30.22.47.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jun 2026 22:47:43 -0700 (PDT) From: Enzo Adriano To: Yuanshen Cao , Andre Przywara Cc: conor+dt@kernel.org, mripard@kernel.org, krzk+dt@kernel.org, robh@kernel.org, samuel@sholland.org, wens@kernel.org, jernej.skrabec@gmail.com, Frank.Li@kernel.org, vkoul@kernel.org, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Frank Li Subject: Re: [PATCH v3 1/5] dmaengine: sun6i-dma: Refactor to support A733 interrupt and register handling Date: Wed, 1 Jul 2026 01:47:01 -0400 Message-ID: <20260701054701.3961908-1-enzo.adriano.code@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: <20260622-sun60i-a733-dma-v3-0-f697ef296cbc@gmail.com> <20260622-sun60i-a733-dma-v3-1-f697ef296cbc@gmail.com> <20260629003505.18f0053d@ryzen.lan> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Yuanshen, Andre, I applied the v3 series locally on top of dc59e4fea9d8. The series applied cleanly, the focused DMA binding check passed, and a focused drivers/dma/sun6i-dma.o build passed. I have not done a hardware DMA runtime test, so this is only static review plus build/schema validation. On the IRQ accessor shape, I think Andre's data-driven direction is a good fit for the enable/status register differences. The A733-specific values look like data: enable offset 0x134, status offset 0x138, stride 0x40. A small helper using cfg offsets/stride would keep the call sites readable without needing per-compatible read/write accessors. I would keep dump_com_regs separate unless there is a clean table-driven way to express the genuinely different dump layout. While comparing this with the public Sun60iw2 BSP, I think the same respin should also fix the interrupt channel decode path that Sashiko pointed out. The series encodes the interrupt register as: irq_reg = pchan->idx / sdev->cfg->num_channels_per_reg; irq_offset = pchan->idx % sdev->cfg->num_channels_per_reg; but the interrupt handler still decodes with: pchan = sdev->pchans + j; For A733, num_channels_per_reg is 1, so j is always 0 and each IRQ status register would map back to pchans[0]. The public Sun60iw2 BSP uses the inverse mapping: pchan = sdev->pchans + (i * sdev->cfg->channum_per_reg + j); That matches the encode path and looks like the shape needed here as well. The register-loop bounds probably want the same treatment: derive the number of IRQ status registers from the real channel count, not from an implicitly exact division.