From: Enzo Adriano <enzo.adriano.code@gmail.com>
To: Andre Przywara <andre.przywara@arm.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Chen-Yu Tsai <wens@kernel.org>
Cc: Brian Masney <bmasney@redhat.com>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
Enzo Adriano <enzo.adriano.code@gmail.com>,
Sashiko <sashiko-bot@kernel.org>
Subject: [PATCH RFT 2/2] clk: sunxi-ng: a523: use single-divider clock helpers
Date: Wed, 12 Aug 2026 16:15:02 -0400 [thread overview]
Message-ID: <20260812201502.264919-3-enzo.adriano.code@gmail.com> (raw)
In-Reply-To: <20260812201502.264919-1-enzo.adriano.code@gmail.com>
The A523 MBUS, IOMMU, and DRAM clocks have an M divider but no P
divider, while HSTIMER0-5 and R-TIMER0-2 have a P divider but no M
divider. They currently use the two-divider ccu_mp class by declaring
the missing field with width zero.
ccu_mp_set_rate() unconditionally masks both divider fields, so a zero
width forms an invalid GENMASK() range and can clear unrelated register
bits. The M-only clocks also require the hardware update bit, which
ccu_mp operations do not handle.
Use the single-divider M helper for MBUS, IOMMU, and DRAM, and the
power-of-two P helper for the timer clocks. Preserve the parents,
registers, real divider fields, muxes, gates, clock flags, and
update-bit features.
Reported-by: Sashiko <sashiko-bot@kernel.org>
Link: https://lore.kernel.org/r/20260722010926.0A8B01F000E9@smtp.kernel.org
Link: https://lore.kernel.org/r/20260712081341.9D1431F00A3D@smtp.kernel.org
Suggested-by: Chen-Yu Tsai <wens@kernel.org>
Fixes: 6702d17f54a8 ("clk: sunxi-ng: a523: add video mod clocks")
Fixes: 74b0443a0d0a ("clk: sunxi-ng: a523: add system mod clocks")
Fixes: 8cea339cfb81 ("clk: sunxi-ng: add support for the A523/T527 PRCM CCU")
Link: https://lore.kernel.org/r/CAGb2v67GDBTq8vdxNxBfNVSe=oStcgaJzm0ig2WAEXNQSkVa1g@mail.gmail.com
Link: https://lore.kernel.org/r/20260723004856.55158e84@ryzen.lan
Assisted-by: Codex:gpt-5
Signed-off-by: Enzo Adriano <enzo.adriano.code@gmail.com>
---
not tested on A523/T527 hardware; testing on actual hardware is needed.
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c | 37 +++---
drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 136 +++++++++++------------
2 files changed, 82 insertions(+), 91 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c b/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
index db0e36d8838e74..349230e28c1c3a 100644
--- a/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
@@ -43,27 +43,24 @@ static SUNXI_CCU_M_DATA_WITH_MUX(r_apb1_clk, "r-apb1",
24, 3, /* mux */
0);
-static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer0, "r-timer0",
- r_ahb_apb_parents, 0x100,
- 0, 0, /* no M */
- 1, 3, /* P */
- 4, 3, /* mux */
- BIT(0),
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer0, "r-timer0",
+ r_ahb_apb_parents, 0x100,
+ 1, 3, /* P */
+ 4, 3, /* mux */
+ BIT(0),
+ 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer1, "r-timer1",
+ r_ahb_apb_parents, 0x104,
+ 1, 3, /* P */
+ 4, 3, /* mux */
+ BIT(0),
+ 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer2, "r-timer2",
+ r_ahb_apb_parents, 0x108,
+ 1, 3, /* P */
+ 4, 3, /* mux */
+ BIT(0),
0);
-static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer1, "r-timer1",
- r_ahb_apb_parents, 0x104,
- 0, 0, /* no M */
- 1, 3, /* P */
- 4, 3, /* mux */
- BIT(0),
- 0);
-static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer2, "r-timer2",
- r_ahb_apb_parents, 0x108,
- 0, 0, /* no M */
- 1, 3, /* P */
- 4, 3, /* mux */
- BIT(0),
- 0);
static SUNXI_CCU_GATE_HW(bus_r_timer_clk, "bus-r-timer", &r_ahb_clk.common.hw,
0x11c, BIT(0), 0);
diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
index 20dad06b37ca31..5c632e475aaa04 100644
--- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
+++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
@@ -380,14 +380,14 @@ static const struct clk_parent_data mbus_parents[] = {
{ .hw = &pll_periph1_150M_clk.hw },
{ .fw_name = "hosc" },
};
-static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents,
- 0x540,
- 0, 5, /* M */
- 0, 0, /* no P */
- 24, 3, /* mux */
- BIT(31), /* gate */
- CLK_IS_CRITICAL,
- CCU_FEATURE_UPDATE_BIT);
+
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents,
+ 0x540,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ CLK_IS_CRITICAL,
+ CCU_FEATURE_UPDATE_BIT);
static const struct clk_hw *mbus_hws[] = { &mbus_clk.common.hw };
@@ -513,58 +513,53 @@ static const struct clk_parent_data hstimer_parents[] = {
{ .fw_name = "losc" },
{ .hw = &pll_periph0_200M_clk.hw },
};
-static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer0_clk, "hstimer0",
- hstimer_parents, 0x730,
- 0, 0, /* M */
- 0, 3, /* P */
- 24, 3, /* mux */
- BIT(31), /* gate */
- 0);
-static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer1_clk, "hstimer1",
- hstimer_parents,
- 0x734,
- 0, 0, /* M */
- 0, 3, /* P */
- 24, 3, /* mux */
- BIT(31), /* gate */
- 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(hstimer0_clk, "hstimer0",
+ hstimer_parents, 0x730,
+ 0, 3, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
-static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer2_clk, "hstimer2",
- hstimer_parents,
- 0x738,
- 0, 0, /* M */
- 0, 3, /* P */
- 24, 3, /* mux */
- BIT(31), /* gate */
- 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(hstimer1_clk, "hstimer1",
+ hstimer_parents,
+ 0x734,
+ 0, 3, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
-static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer3_clk, "hstimer3",
- hstimer_parents,
- 0x73c,
- 0, 0, /* M */
- 0, 3, /* P */
- 24, 3, /* mux */
- BIT(31), /* gate */
- 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(hstimer2_clk, "hstimer2",
+ hstimer_parents,
+ 0x738,
+ 0, 3, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
-static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer4_clk, "hstimer4",
- hstimer_parents,
- 0x740,
- 0, 0, /* M */
- 0, 3, /* P */
- 24, 3, /* mux */
- BIT(31), /* gate */
- 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(hstimer3_clk, "hstimer3",
+ hstimer_parents,
+ 0x73c,
+ 0, 3, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
-static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer5_clk, "hstimer5",
- hstimer_parents,
- 0x744,
- 0, 0, /* M */
- 0, 3, /* P */
- 24, 3, /* mux */
- BIT(31), /* gate */
- 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(hstimer4_clk, "hstimer4",
+ hstimer_parents,
+ 0x740,
+ 0, 3, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(hstimer5_clk, "hstimer5",
+ hstimer_parents,
+ 0x744,
+ 0, 3, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
static SUNXI_CCU_GATE_HWS(bus_hstimer_clk, "bus-hstimer", ahb_hws, 0x74c,
BIT(0), 0);
@@ -584,14 +579,13 @@ static const struct clk_parent_data iommu_parents[] = {
{ .fw_name = "hosc" },
};
-static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(iommu_clk, "iommu", iommu_parents,
- 0x7b0,
- 0, 5, /* M */
- 0, 0, /* no P */
- 24, 3, /* mux */
- BIT(31), /* gate */
- CLK_SET_RATE_PARENT,
- CCU_FEATURE_UPDATE_BIT);
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(iommu_clk, "iommu", iommu_parents,
+ 0x7b0,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ CLK_SET_RATE_PARENT,
+ CCU_FEATURE_UPDATE_BIT);
static SUNXI_CCU_GATE_HWS(bus_iommu_clk, "bus-iommu", apb0_hws, 0x7bc,
BIT(0), 0);
@@ -603,14 +597,14 @@ static const struct clk_parent_data dram_parents[] = {
{ .hw = &pll_periph0_400M_clk.hw },
{ .hw = &pll_periph0_150M_clk.hw },
};
-static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(dram_clk, "dram", dram_parents,
- 0x800,
- 0, 5, /* M */
- 0, 0, /* no P */
- 24, 3, /* mux */
- BIT(31), /* gate */
- CLK_IS_CRITICAL,
- CCU_FEATURE_UPDATE_BIT);
+
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(dram_clk, "dram", dram_parents,
+ 0x800,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ CLK_IS_CRITICAL,
+ CCU_FEATURE_UPDATE_BIT);
static SUNXI_CCU_GATE_HWS(mbus_dma_clk, "mbus-dma", mbus_hws,
0x804, BIT(0), 0);
--
2.53.0
prev parent reply other threads:[~2026-08-12 20:15 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-22 0:56 [PATCH] clk: sunxi-ng: ccu_mp: fix clocks without P dividers Enzo Adriano
2026-07-22 1:09 ` sashiko-bot
2026-07-22 9:24 ` Andre Przywara
2026-07-22 13:27 ` Chen-Yu Tsai
2026-07-22 17:37 ` Enzo Adriano
2026-07-22 17:43 ` Chen-Yu Tsai
2026-07-22 22:48 ` Andre Przywara
2026-08-12 20:15 ` [PATCH RFT 0/2] clk: sunxi-ng: fix A523/T527 single-divider clocks Enzo Adriano
2026-08-12 20:15 ` [PATCH RFT 1/2] clk: sunxi-ng: add feature-aware M divider helper Enzo Adriano
2026-08-12 20:15 ` Enzo Adriano [this message]
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