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[9.244.8.156]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4d423604f7fsm1137266b6e.7.2026.09.21.13.05.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2026 13:05:14 -0700 (PDT) From: Enzo Adriano To: junhui.liu@pigmoral.tech Cc: Stephen Boyd , Brian Masney , Jerome Brunet , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 7/8] clk: sunxi-ng: a733: Add bus clock gates Date: Mon, 21 Sep 2026 16:05:12 -0400 Message-ID: <20260921200512.3179109-1-enzo.adriano.code@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260921-a733-clk-v4-7-9c184ebe9ac1@pigmoral.tech> References: <20260921-a733-clk-v4-0-9c184ebe9ac1@pigmoral.tech> <20260921-a733-clk-v4-7-9c184ebe9ac1@pigmoral.tech> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Junhui, I tested the exact v4 series on a Radxa Cubie A7S. I used v7.3-rc1, applied the four-patch A523 single-divider prerequisite, this eight-patch series, and Andre's current seven-patch A733 pinctrl series. The test DT is a minimal Cubie A7S harness with the main and R CCUs, RTC, pinctrl, UART0, and MMC0. The Image, DTB, and initramfs were loaded into RAM from U-Boot. The exact posted stack starts all eight CPUs, probes the RTC and the A733 pinctrl driver, and binds UART0. Serial output then stops immediately after the 8250 driver replaces the boot console: sun60i-a733-pinctrl 2000000.pinctrl: initialized sunXi PIO driver printk: console [ttyS0] disabled 2500000.serial: ttyS0 MMIO32:0x0000000002500000 ... is a 16550A printk: console [ttyS0] enabled printk: legacy bootconsole [uart8250] disabled It never reaches the initramfs `/bin/sh` readiness line. There is no panic or oops in the captured output. As a private comparator, I changed only `ahb_cpus_clk` at 0x5c0 bit 28 to `CLK_IS_CRITICAL`. That advances the same build to: clk: Disabling unused clocks but serial output stops there and PID 1 is still not reached. I also added private begin/done tracing around each individual enabled clock in `clk_disable_unused_subtree()`. Neither trace marker appears, so the second loss occurs before the first individual unused-clock disable is attempted. Each run used the same RAM-only payload and was followed by an identity-checked 120-second power recovery. The board returned to its exact vendor kernel and eMMC root after all three runs. So I cannot add a Tested-by for v4 as posted. The `ahb-cpus` gate appears to be one issue, but marking it critical is not sufficient on this board. Could you please check the CPUS/AHB dependency and the path entered immediately after `clk: Disabling unused clocks`? I can retest a focused change or v5 on the Cubie A7S. Assisted-by: Codex:gpt-5 I reviewed this report and take responsibility for its contents. Regards, Enzo