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[78.137.176.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae5c8a44sm177243566b.20.2026.09.23.13.23.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 13:23:15 -0700 (PDT) From: Pablo Mazzini To: Chen-Yu Tsai , Conor Dooley , Jernej Skrabec , Krzysztof Kozlowski , Rob Herring , Russell King , Samuel Holland Cc: Pablo Mazzini , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v1 11/11] ARM: sunxi: add B288 and the PocketBook Verse board Date: Wed, 23 Sep 2026 21:17:01 +0100 Message-ID: <20260923201701.43391-11-pmazzini@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260923201701.43391-1-pmazzini@gmail.com> References: <20260923201701.43391-1-pmazzini@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit arm,cpu-registers-not-fw-configured is required: Allwinner's boot0 sets neither CNTFRQ nor CNTVOFF, so the virtual timer storms. Same reason as commit 121b96cd9d7e ("ARM: sun6i: Enable ARM arch timers"). The watchdog interrupt was measured on hardware via GICD_ISPENDR. Signed-off-by: Pablo Mazzini --- arch/arm/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun8i-b288-pocketbook-verse.dts | 122 +++++++ arch/arm/boot/dts/allwinner/sun8i-b288.dtsi | 300 ++++++++++++++++++ arch/arm/mach-sunxi/sunxi.c | 1 + 4 files changed, 424 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-b288-pocketbook-verse.dts create mode 100644 arch/arm/boot/dts/allwinner/sun8i-b288.dtsi diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile index 75b2b6a2f7a6..2dfdc01e4825 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -227,6 +227,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a83t-bananapi-m3.dtb \ sun8i-a83t-cubietruck-plus.dtb \ sun8i-a83t-tbs-a711.dtb \ + sun8i-b288-pocketbook-verse.dtb \ sun8i-h2-plus-bananapi-m2-zero.dtb \ sun8i-h2-plus-libretech-all-h3-cc.dtb \ sun8i-h2-plus-orangepi-r1.dtb \ diff --git a/arch/arm/boot/dts/allwinner/sun8i-b288-pocketbook-verse.dts b/arch/arm/boot/dts/allwinner/sun8i-b288-pocketbook-verse.dts new file mode 100644 index 000000000000..91c89d5a097e --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-b288-pocketbook-verse.dts @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * PocketBook Verse (PB629), an Allwinner B288 based e-reader. + */ + +/dts-v1/; +#include "sun8i-b288.dtsi" + +#include + +/ { + model = "PocketBook Verse"; + compatible = "pocketbook,verse", "allwinner,sun8i-b288"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x20000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dldo2>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc3 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dldo1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&pio { + vcc-pc-supply = <®_dldo1>; + vcc-pd-supply = <®_dldo1>; + /* + * PC and PD are named in the vendor rail list; PF is not. It is not + * on dldo2: with that rail off, a pull-up on PF6 still reads card + * detect correctly, so the bank has its own supply. dcdc1 is the + * only remaining candidate, carrying vcc-io and vcc-card. Derived + * from the rail naming plus that measurement, not from a schematic. + */ + vcc-pf-supply = <®_dcdc1>; +}; + +&i2c0 { + status = "okay"; + + axp22x: pmic@34 { + compatible = "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1260000>; + regulator-max-microvolt = <1260000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vcc-dram"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pc"; +}; + +®_dldo2 { + /* Powers the microSD slot (slot pin 4), switched per card scan. */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-sdcv"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-b288.dtsi b/arch/arm/boot/dts/allwinner/sun8i-b288.dtsi new file mode 100644 index 000000000000..58668d581368 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-b288.dtsi @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Allwinner B288 (sun8iw10p1) SoC + * + * Addresses and interrupts come from the PocketBook Verse (PB629) vendor + * device tree, cross-checked against the BSP clk-sun8iw10.c. + */ + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + clocks { + osc24M: osc24M-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + arm,cpu-registers-not-fw-configured; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * mmc0 is a v4p1x controller, so it runs in the old timing + * mode and needs the sample and output phase clocks. Do not + * give it the sun50i-a64-mmc fallback: that selects the new + * timing mode, which this block does not implement. + */ + nmi_intc: interrupt-controller@1c000d0 { + compatible = "allwinner,sun8i-b288-nmi", + "allwinner,sun9i-a80-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c000d0 0x0c>; + interrupts = ; + }; + + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun8i-b288-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_SDMMC0_BUS>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* SDXC v4.5. The soldered eMMC; shares the PC pads with mmc2. */ + mmc3: mmc@1c12000 { + compatible = "allwinner,sun8i-b288-emmc", + "allwinner,sun50i-a64-emmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ccu CLK_BUS_SDMMC3_BUS>, <&ccu CLK_MMC3>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC3>; + reset-names = "ahb"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* + * mmc2 (0x01c11000) is an SDHCI-style controller, not SDXC, and + * has no upstream binding. It loses the PC pad arbitration to + * mmc3 and is unused here, so it is left undescribed rather than + * given a wrong compatible. + */ + + ccu: clock-controller@1c20000 { + compatible = "allwinner,sun8i-b288-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + rtc: rtc@1c20400 { + compatible = "allwinner,sun8i-b288-rtc"; + reg = <0x01c20400 0x400>; + interrupts = ; + clock-output-names = "osc32k"; + clocks = <&osc32k>; + #clock-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,sun8i-b288-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = , + , + , + ; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + function = "sdc0"; + drive-strength = <30>; + bias-pull-up; + }; + + i2c0_pins: i2c0-pins { + pins = "PB6", "PB7"; + function = "twi0"; + }; + + mmc3_pins: mmc3-pins { + pins = "PC1", "PC4", "PC5", "PC6", + "PC7", "PC8", "PC9", "PC10", + "PC11", "PC12", "PC13", "PC14"; + function = "sdc3"; + drive-strength = <40>; + bias-pull-up; + }; + + uart0_pb_pins: uart0-pb-pins { + pins = "PB4", "PB5"; + function = "uart0"; + }; + }; + + wdt: watchdog@1c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = ; + clocks = <&osc24M>; + }; + + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial@1c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun8i-b288-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_TWI0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun8i-b288-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_TWI1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun8i-b288-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_TWI2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +}; diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index e1b7945aac99..c5b19d0e63f9 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -61,6 +61,7 @@ MACHINE_END static const char * const sun8i_board_dt_compat[] = { "allwinner,sun8i-a23", "allwinner,sun8i-a33", + "allwinner,sun8i-b288", "allwinner,sun8i-h2-plus", "allwinner,sun8i-h3", "allwinner,sun8i-r40", -- 2.53.0