Re: [PATCH v1 04/11] pinctrl: sunxi: add Allwinner B288 pin controller driver

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] pinctrl: sunxi: IRQ index collision for pin G3
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commit fdee02e8823a26621c358b63abf2ff74202265b9
Author: Pablo Mazzini <pmazzini@gmail.com>

pinctrl: sunxi: add Allwinner B288 pin controller driver

This commit adds the pin controller and GPIO support for the Allwinner B288
SoC, covering 78 pins across ports B, C, D, F, and G, including four banks
of external interrupt capable pins.

> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c
> new file mode 100644
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c

[ ... ]

> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "pwm7"),
> +		  SUNXI_FUNCTION(0x3, "dmic0"),
> +		  SUNXI_FUNCTION(0x4, "spi1"),
> +		  SUNXI_FUNCTION(0x5, "sdc1"),
> +		  SUNXI_FUNCTION(0x7, "io_disabled"),
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)),
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "twi1"),
> +		  SUNXI_FUNCTION(0x3, "dmic0"),
> +		  SUNXI_FUNCTION(0x4, "spi1"),
> +		  SUNXI_FUNCTION(0x5, "sdc1"),
> +		  SUNXI_FUNCTION(0x7, "io_disabled"),
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)),
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "twi1"),
> +		  SUNXI_FUNCTION(0x3, "dmic0"),
> +		  SUNXI_FUNCTION(0x4, "spi1"),
> +		  SUNXI_FUNCTION(0x5, "sdc1"),
> +		  SUNXI_FUNCTION(0x7, "io_disabled"),
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)),

[Severity: Medium]
Does this incorrectly assign IRQ index 1 instead of 3 for pin G3?

It looks like SUNXI_FUNCTION_IRQ_BANK is assigning IRQ index 1 for pin G3 in
the sun8i_b288_pins array, which collides with the IRQ mapping for pin G1
defined earlier. This could cause external interrupts on G3 to be incorrectly
routed or to conflict with G1.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260923201701.43391-1-pmazzini@gmail.com?part=4