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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45a1a509b9bsm6560505e9.6.2025.08.13.08.27.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Aug 2025 08:27:08 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Chen-Yu Tsai Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: Re: [PATCH net-next v2 07/10] arm64: dts: allwinner: a527: cubie-a5e: Enable second Ethernet port Date: Wed, 13 Aug 2025 17:27:06 +0200 Message-ID: <2376533.ElGaqSPkdT@jernej-laptop> In-Reply-To: <20250813145540.2577789-8-wens@kernel.org> References: <20250813145540.2577789-1-wens@kernel.org> <20250813145540.2577789-8-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne sreda, 13. avgust 2025 ob 16:55:37 Srednjeevropski poletni =C4=8Das je = Chen-Yu Tsai napisal(a): > From: Chen-Yu Tsai >=20 > On the Radxa Cubie A5E board, the second Ethernet controller, aka the > GMAC200, is connected to a second external Maxio MAE0621A PHY. The PHY > uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to > its reset pin. >=20 > Enable the second Ethernet port. Also fix up the label for the existing > external PHY connected to the first Ethernet port. An enable delay for the > PHY supply regulator is added to make sure the PHY's internal regulators > are fully powered and the PHY is operational. >=20 > Signed-off-by: Chen-Yu Tsai Acked-by: Jernej Skrabec Best regards, Jernej > --- >=20 > Changes since v1: > - Switch to generic (tx|rx)-internal-delay-ps properties > - Add PHY regulator delay > --- > .../dts/allwinner/sun55i-a527-cubie-a5e.dts | 28 +++++++++++++++++-- > 1 file changed, 26 insertions(+), 2 deletions(-) >=20 > diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/ar= ch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts > index d4cee2222104..e96a419faf21 100644 > --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts > +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts > @@ -14,6 +14,7 @@ / { > =20 > aliases { > ethernet0 =3D &gmac0; > + ethernet1 =3D &gmac1; > serial0 =3D &uart0; > }; > =20 > @@ -76,7 +77,7 @@ &ehci1 { > =20 > &gmac0 { > phy-mode =3D "rgmii-id"; > - phy-handle =3D <&ext_rgmii_phy>; > + phy-handle =3D <&ext_rgmii0_phy>; > phy-supply =3D <®_cldo3>; > =20 > allwinner,tx-delay-ps =3D <300>; > @@ -85,13 +86,24 @@ &gmac0 { > status =3D "okay"; > }; > =20 > +&gmac1 { > + phy-mode =3D "rgmii-id"; > + phy-handle =3D <&ext_rgmii1_phy>; > + phy-supply =3D <®_cldo4>; > + > + tx-internal-delay-ps =3D <300>; > + rx-internal-delay-ps =3D <400>; > + > + status =3D "okay"; > +}; > + > &gpu { > mali-supply =3D <®_dcdc2>; > status =3D "okay"; > }; > =20 > &mdio0 { > - ext_rgmii_phy: ethernet-phy@1 { > + ext_rgmii0_phy: ethernet-phy@1 { > compatible =3D "ethernet-phy-ieee802.3-c22"; > reg =3D <1>; > reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ > @@ -100,6 +112,16 @@ ext_rgmii_phy: ethernet-phy@1 { > }; > }; > =20 > +&mdio1 { > + ext_rgmii1_phy: ethernet-phy@1 { > + compatible =3D "ethernet-phy-ieee802.3-c22"; > + reg =3D <1>; > + reset-gpios =3D <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ > + reset-assert-us =3D <10000>; > + reset-deassert-us =3D <150000>; > + }; > +}; > + > &mmc0 { > vmmc-supply =3D <®_cldo3>; > cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ > @@ -240,6 +262,8 @@ reg_cldo4: cldo4 { > regulator-min-microvolt =3D <3300000>; > regulator-max-microvolt =3D <3300000>; > regulator-name =3D "vcc-pj-phy"; > + /* enough time for the PHY to fully power on */ > + regulator-enable-ramp-delay =3D <150000>; > }; > =20 > reg_cpusldo: cpusldo { >=20