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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f258f0597sm25364929f8f.42.2025.02.22.01.46.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Feb 2025 01:46:21 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland , Ryan Walklin Cc: Andre Przywara , Chris Morgan , Hironori KIKUCHI , Philippe Simons , linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Ryan Walklin Subject: Re: [PATCH 7/8] arm64: dts: allwinner: rg35xx: Enable LCD output Date: Sat, 22 Feb 2025 10:46:19 +0100 Message-ID: <23840170.6Emhk5qWAg@jernej-laptop> In-Reply-To: <20250216092827.15444-8-ryan@testtoast.com> References: <20250216092827.15444-1-ryan@testtoast.com> <20250216092827.15444-8-ryan@testtoast.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne nedelja, 16. februar 2025 ob 10:27:14 Srednjeevropski standardni =C4=8D= as je Ryan Walklin napisal(a): > The RG35XX has a 640x480 RGB/SPI LCD panel, supported by the SoC display > pipeline and an NV3052C controller. The H616 SOC's GPIO bank D contains > the muxed display pins for RGB and LVDS output support. >=20 > Enable the display engine and LCD timing controller, configure the > panel, and add a fixed 3.3v GPIO-controlled regulator for the panel, and > a VCC supply for the display pins as per the other GPIO banks. >=20 > Signed-off-by: Ryan Walklin > --- > .../sun50i-h700-anbernic-rg35xx-2024.dts | 58 +++++++++++++++++++ > 1 file changed, 58 insertions(+) >=20 > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-20= 24.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts > index a231abf1684ad..388487d4720e2 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts > @@ -175,6 +175,49 @@ reg_vcc5v: regulator-vcc5v { /* USB-C power input */ > regulator-min-microvolt =3D <5000000>; > regulator-max-microvolt =3D <5000000>; > }; > + > + reg_lcd: regulator-gpio-lcd-vdd { > + compatible =3D "regulator-fixed"; > + regulator-min-microvolt =3D <3300000>; > + regulator-max-microvolt =3D <3300000>; > + regulator-name =3D "vdd-lcd"; > + gpio =3D <&pio 8 15 GPIO_ACTIVE_HIGH>; // PI15 > + enable-active-high; > + }; > + > + spi_lcd: spi { > + compatible =3D "spi-gpio"; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + sck-gpios =3D <&pio 8 9 GPIO_ACTIVE_HIGH>; // PI9 > + mosi-gpios =3D <&pio 8 10 GPIO_ACTIVE_HIGH>; // PI10 > + cs-gpios =3D <&pio 8 8 GPIO_ACTIVE_HIGH>; // PI8 > + num-chipselects =3D <1>; > + > + panel: panel@0 { > + compatible =3D "anbernic,rg35xx-plus-panel"; > + > + reg =3D <0>; > + > + spi-max-frequency =3D <3125000>; > + spi-3wire; > + > + reset-gpios =3D <&pio 8 14 GPIO_ACTIVE_LOW>; // PI14 > + > + backlight =3D <&backlight>; There is no backlight node at this point. Reverse patches 7 and 8 or better= yet, merge them and put patch 8 message into comment to backlight node. Best regards, Jernej > + power-supply =3D <®_lcd>; > + > + pinctrl-0 =3D <&lcd0_rgb888_pins>; > + pinctrl-names =3D "default"; > + > + port { > + panel_in_rgb: endpoint { > + remote-endpoint =3D <&tcon_lcd0_out_lcd>; > + }; > + }; > + }; > + }; > }; > =20 > &codec { > @@ -187,6 +230,10 @@ &cpu0 { > cpu-supply =3D <®_dcdc1>; > }; > =20 > +&de { > + status =3D "okay"; > +}; > + > &ehci0 { > status =3D "okay"; > }; > @@ -206,6 +253,7 @@ &ohci0 { > &pio { > vcc-pa-supply =3D <®_cldo3>; > vcc-pc-supply =3D <®_cldo3>; > + vcc-pd-supply =3D <®_cldo3>; > vcc-pe-supply =3D <®_cldo3>; > vcc-pf-supply =3D <®_cldo3>; > vcc-pg-supply =3D <®_aldo4>; > @@ -355,3 +403,13 @@ &usbotg { > &usbphy { > status =3D "okay"; > }; > + > +&tcon_lcd0 { > + status =3D "okay"; > +}; > + > +&tcon_lcd0_out { > + tcon_lcd0_out_lcd: endpoint@1 { > + remote-endpoint =3D <&panel_in_rgb>; > + }; > +}; >=20