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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b031c5casm78071995e9.39.2025.02.23.05.57.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Feb 2025 05:57:47 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Samuel Holland , "open list:COMMON CLK FRAMEWORK" , "moderated list:ARM/Allwinner sunXi SoC support" , "open list:ARM/Allwinner sunXi SoC support" , open list , Philippe Simons Cc: Philippe Simons , Andre Przywara Subject: Re: [PATCH v3 1/1] clk: sunxi-ng: h616: Reparent GPU clock during frequency changes Date: Sun, 23 Feb 2025 14:57:46 +0100 Message-ID: <2716580.BddDVKsqQX@jernej-laptop> In-Reply-To: <3297157.aV6nBDHxoP@jernej-laptop> References: <20250220113808.1122414-1-simons.philippe@gmail.com> <20250220113808.1122414-2-simons.philippe@gmail.com> <3297157.aV6nBDHxoP@jernej-laptop> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne =C4=8Detrtek, 20. februar 2025 ob 16:41:54 Srednjeevropski standardni = =C4=8Das je Jernej =C5=A0krabec napisal(a): > Dne =C4=8Detrtek, 20. februar 2025 ob 12:38:08 Srednjeevropski standardni= =C4=8Das je Philippe Simons napisal(a): > > The H616 manual does not state that the GPU PLL supports > > dynamic frequency configuration, so we must take extra care when changi= ng > > the frequency. Currently any attempt to do device DVFS on the GPU lead > > to panfrost various ooops, and GPU hangs. > >=20 > > The manual describes the algorithm for changing the PLL > > frequency, which the CPU PLL notifier code already support, so we reuse > > that to reparent the GPU clock to GPU1 clock during frequency > > changes. > >=20 > > Signed-off-by: Philippe Simons > > Reviewed-by: Andre Przywara > > --- > > drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 36 +++++++++++++++++++++++++- > > 1 file changed, 35 insertions(+), 1 deletion(-) >=20 > Changelog is missing here. What's changed? >=20 > In any case, this patch isn't useful on its own. What about PPU and GPU D= T node? In the light of separate PPU & GPU DT series, this patch is gtg. Reviewed-by: Jernej Skrabec Best regards, Jernej =20 > >=20 > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi= =2Dng/ccu-sun50i-h616.c > > index 190816c35..6050cbfa9 100644 > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c > > @@ -328,10 +328,16 @@ static SUNXI_CCU_M_WITH_MUX_GATE(gpu0_clk, "gpu0"= , gpu0_parents, 0x670, > > 24, 1, /* mux */ > > BIT(31), /* gate */ > > CLK_SET_RATE_PARENT); > > + > > +/* > > + * This clk is needed as a temporary fall back during GPU PLL freq cha= nges. > > + * Set CLK_IS_CRITICAL flag to prevent from being disabled. > > + */ > > +#define SUN50I_H616_GPU_CLK1_REG 0x674 > > static SUNXI_CCU_M_WITH_GATE(gpu1_clk, "gpu1", "pll-periph0-2x", 0x674, > > 0, 2, /* M */ > > BIT(31),/* gate */ > > - 0); > > + CLK_IS_CRITICAL); > > =20 > > static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2", > > 0x67c, BIT(0), 0); > > @@ -1120,6 +1126,19 @@ static struct ccu_pll_nb sun50i_h616_pll_cpu_nb = =3D { > > .lock =3D BIT(28), > > }; > > =20 > > +static struct ccu_mux_nb sun50i_h616_gpu_nb =3D { > > + .common =3D &gpu0_clk.common, > > + .cm =3D &gpu0_clk.mux, > > + .delay_us =3D 1, /* manual doesn't really say */ > > + .bypass_index =3D 1, /* GPU_CLK1@400MHz */ > > +}; > > + > > +static struct ccu_pll_nb sun50i_h616_pll_gpu_nb =3D { > > + .common =3D &pll_gpu_clk.common, > > + .enable =3D BIT(29), /* LOCK_ENABLE */ > > + .lock =3D BIT(28), > > +}; > > + > > static int sun50i_h616_ccu_probe(struct platform_device *pdev) > > { > > void __iomem *reg; > > @@ -1170,6 +1189,14 @@ static int sun50i_h616_ccu_probe(struct platform= _device *pdev) > > val |=3D BIT(0); > > writel(val, reg + SUN50I_H616_PLL_AUDIO_REG); > > =20 > > + /* > > + * Set the input-divider for the gpu1 clock to 3, to reach a safe 400= MHz. > > + */ > > + val =3D readl(reg + SUN50I_H616_GPU_CLK1_REG); > > + val &=3D ~GENMASK(1, 0); > > + val |=3D 2; > > + writel(val, reg + SUN50I_H616_GPU_CLK1_REG); > > + > > /* > > * First clock parent (osc32K) is unusable for CEC. But since there > > * is no good way to force parent switch (both run with same frequenc= y), > > @@ -1190,6 +1217,13 @@ static int sun50i_h616_ccu_probe(struct platform= _device *pdev) > > /* Re-lock the CPU PLL after any rate changes */ > > ccu_pll_notifier_register(&sun50i_h616_pll_cpu_nb); > > =20 > > + /* Reparent GPU during GPU PLL rate changes */ > > + ccu_mux_notifier_register(pll_gpu_clk.common.hw.clk, > > + &sun50i_h616_gpu_nb); > > + > > + /* Re-lock the GPU PLL after any rate changes */ > > + ccu_pll_notifier_register(&sun50i_h616_pll_gpu_nb); > > + > > return 0; > > } > > =20 > >=20 >=20 >=20 >=20 >=20 >=20