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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45f27f44624sm107457145e9.3.2025.09.15.08.52.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 08:52:38 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Lukas Schmid , Andre Przywara Cc: Tom Rini , u-boot@lists.denx.de, "linux-sunxi@lists.linux.dev" , =?UTF-8?B?QW5kcsOhcyBTemVtesWR?= Subject: Re: [PATCH v1 1/1] sunxi: extend R528/T113-s3/D1(s) DRAM initialisation Date: Mon, 15 Sep 2025 17:52:37 +0200 Message-ID: <3006634.e9J7NaK4W3@jernej-laptop> In-Reply-To: <20250915163637.38d05aab@donnerap> References: <20250914144411.157826-1-lukas.schmid@netcube.li> <20250915163637.38d05aab@donnerap> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne ponedeljek, 15. september 2025 ob 17:36:37 Srednjeevropski poletni =C4= =8Das je Andre Przywara napisal(a): > On Sun, 14 Sep 2025 16:44:11 +0200 > Lukas Schmid wrote: >=20 > Hi Lukas, >=20 > thanks for the patch! >=20 > CC:ing the sunxi list and Andr=C3=A1s, who I think has some T113-s4 devic= e as > well. >=20 > It would be good to see some Tested-by: tags, but otherwise the patch > looks good, I'd say. >=20 > Also I hear that awboot uses 0x6800 as the chip ID for the -s4, can > someone shed some light on this? >=20 > Cheers, > Andre >=20 > > Extend the DRAM initialisation code to add support for the T113-S4 aka > > T113M4020DC0 by checking the SoC's CHIPID. > >=20 > > Signed-off-by: Lukas Schmid > > --- > > drivers/ram/sunxi/dram_sun20i_d1.c | 13 ++++++++++++- > > drivers/ram/sunxi/dram_sun20i_d1.h | 7 +++++++ > > 2 files changed, 19 insertions(+), 1 deletion(-) > >=20 > > diff --git a/drivers/ram/sunxi/dram_sun20i_d1.c b/drivers/ram/sunxi/dra= m_sun20i_d1.c > > index a1794032f3b..01d19d5feaa 100644 > > --- a/drivers/ram/sunxi/dram_sun20i_d1.c > > +++ b/drivers/ram/sunxi/dram_sun20i_d1.c > > @@ -54,6 +54,11 @@ static void sid_read_ldoB_cal(const dram_para_t *par= a) > > clrsetbits_le32(0x3000150, 0xff00, reg << 8); > > } > > =20 > > +static u32 sid_read_soc_chipid(void) > > +{ > > + return readl(SUNXI_SID_BASE + 0x00) & 0xffff; > > +} > > + > > static void dram_voltage_set(const dram_para_t *para) > > { > > int vol; > > @@ -663,6 +668,7 @@ static void mctl_phy_ac_remapping(const dram_para_t= *para, > > =20 > > fuse =3D (readl(SUNXI_SID_BASE + 0x28) & 0xf00) >> 8; > > debug("DDR efuse: 0x%x\n", fuse); > > + debug("SoC Chip ID: 0x%08x\n", sid_read_soc_chipid()); > > =20 > > if (para->dram_type =3D=3D SUNXI_DRAM_TYPE_DDR2) { > > if (fuse =3D=3D 15) > > @@ -675,7 +681,12 @@ static void mctl_phy_ac_remapping(const dram_para_= t *para, > > switch (fuse) { > > case 8: cfg =3D ac_remapping_tables[2]; break; > > case 9: cfg =3D ac_remapping_tables[3]; break; > > - case 10: cfg =3D ac_remapping_tables[5]; break; > > + case 10: > > + if (sid_read_soc_chipid() =3D=3D SUNXI_CHIPID_T113M4020DC0) > > + cfg =3D ac_remapping_tables[0]; > > + else > > + cfg =3D ac_remapping_tables[5]; > > + break; This is similar thing to what has been done in H616 DRAM driver, so FWIW: Reviewed-by: Jernej Skrabec Best regards, Jernej > > case 11: cfg =3D ac_remapping_tables[4]; break; > > default: > > case 12: cfg =3D ac_remapping_tables[1]; break; > > diff --git a/drivers/ram/sunxi/dram_sun20i_d1.h b/drivers/ram/sunxi/dra= m_sun20i_d1.h > > index 91383f6cf10..7bd8f67a77a 100644 > > --- a/drivers/ram/sunxi/dram_sun20i_d1.h > > +++ b/drivers/ram/sunxi/dram_sun20i_d1.h > > @@ -19,6 +19,13 @@ enum sunxi_dram_type { > > SUNXI_DRAM_TYPE_LPDDR3 =3D 7, > > }; > > =20 > > +enum sunxi_soc_chipid { > > + SUNXI_CHIPID_F133A =3D 0x5C00, > > + SUNXI_CHIPID_D1S =3D 0x5E00, > > + SUNXI_CHIPID_T113S3 =3D 0x6000, > > + SUNXI_CHIPID_T113M4020DC0 =3D 0x7200, > > +}; > > + > > /* > > * This structure contains a mixture of fixed configuration settings, > > * variables that are used at runtime to communicate settings between >=20 >=20 >=20