From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9E797F3 for ; Thu, 8 Dec 2022 09:11:31 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4AFDDC433C1; Thu, 8 Dec 2022 09:11:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1670490691; bh=eB4ZBzqRKY2P+/+kH7tim6V7TrIqU7mlpztlV40cPFU=; h=Date:From:To:CC:Subject:In-Reply-To:References:From; b=PHwu2bk4WOCZYFh8XO3jtWg/Pqk7EEQQjg33qH6C+4xAIGzOCLb9mTyZPJNKenFKo 22Tz49fpit01wAbYhQoch29pUGvrdFyc56IqREzb/3ZFkO6Ew1hUfM7eljfGv/VKr3 BPmKjO/WI8WMSz7locQd3+fD8Xq6Vov/4VvXJGhgjJdEjC/3QZXno3fpgw10qpapE0 B+KWpPk2e9BtlSulZzHDCwkokUFo24XuJji5J0V3o9ExtUjINHnyL6X8+PsogYCzZO gHndsRDdhhWB8CMm7/VHXWcENBVU4I36xOXK1Ssifwc1kiHf+B6IOw4jZnJRSk/aCA ua3TxYplb88XA== Date: Thu, 08 Dec 2022 10:10:49 +0100 From: Conor Dooley To: Samuel Holland , Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , linux-riscv@lists.infradead.org CC: Jisheng Zhang , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski , Rob Herring , Heiko Stuebner , linux-arm-kernel@lists.infradead.org, Andre Przywara , Palmer Dabbelt , Guo Ren Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v3_11/12=5D_riscv=3A_Add_the?= =?US-ASCII?Q?_Allwinner_SoC_family_Kconfig_option?= User-Agent: K-9 Mail for Android In-Reply-To: <20221208090237.20572-12-samuel@sholland.org> References: <20221208090237.20572-1-samuel@sholland.org> <20221208090237.20572-12-samuel@sholland.org> Message-ID: <3480FA50-B88E-4BD9-8E9F-27F231C2BAC6@kernel.org> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Acked-by: Conor Dooley On 8 December 2022 10:02:36 GMT+01:00, Samuel Holland wrote: >Allwinner manufactures the sunxi family of application processors=2E This >includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8 >SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs=2E > >The first SoC in the sun20i series is D1, containing a single T-HEAD >C906 core=2E D1s is a low-pin-count variant of D1 with co-packaged DRAM= =2E > >Most peripherals are shared across the entire chip family=2E In fact, the >ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible >with the D1s=2E > >This means many existing device drivers can be reused=2E To facilitate >this reuse, name the symbol ARCH_SUNXI, since that is what the existing >drivers have as their dependency=2E > >Acked-by: Palmer Dabbelt >Reviewed-by: Guo Ren >Reviewed-by: Heiko Stuebner >Tested-by: Heiko Stuebner >Signed-off-by: Samuel Holland >--- > >Changes in v3: > - ARCH_SUNXI depends on MMU && !XIP_KERNEL > >Changes in v2: > - Sort Kconfig as if we had done s/SOC_/ARCH_/ for future-proofing > > arch/riscv/Kconfig=2Esocs | 10 ++++++++++ > 1 file changed, 10 insertions(+) > >diff --git a/arch/riscv/Kconfig=2Esocs b/arch/riscv/Kconfig=2Esocs >index 69774bb362d6=2E=2Ef655dea86d69 100644 >--- a/arch/riscv/Kconfig=2Esocs >+++ b/arch/riscv/Kconfig=2Esocs >@@ -26,6 +26,16 @@ config SOC_STARFIVE > help > This enables support for StarFive SoC platform hardware=2E >=20 >+config ARCH_SUNXI >+ bool "Allwinner sun20i SoCs" >+ depends on MMU && !XIP_KERNEL >+ select ERRATA_THEAD >+ select SIFIVE_PLIC >+ select SUN4I_TIMER >+ help >+ This enables support for Allwinner sun20i platform hardware, >+ including boards based on the D1 and D1s SoCs=2E >+ > config SOC_VIRT > bool "QEMU Virt Machine" > select CLINT_TIMER if RISCV_M_MODE