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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9efc90sm7763650f8f.98.2025.03.23.05.36.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 05:36:11 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Tom Rini , Andre Przywara Cc: Simon Glass , Mikhail Kalashnikov , u-boot@lists.denx.de, linux-sunxi@lists.linux.dev Subject: Re: [PATCH 29/34] sunxi: sun50i_h6: add A523 SPL clock setup code Date: Sun, 23 Mar 2025 13:36:11 +0100 Message-ID: <3536548.QJadu78ljV@jernej-laptop> In-Reply-To: <20250323113544.7933-30-andre.przywara@arm.com> References: <20250323113544.7933-1-andre.przywara@arm.com> <20250323113544.7933-30-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne nedelja, 23. marec 2025 ob 12:35:39 Srednjeevropski standardni =C4=8Das= je Andre Przywara napisal(a): > From: Jernej Skrabec I'm sure you can take credit for this as it's just making definitions and putting them in place. But I can also provide SoB if you want. >=20 > --- > .../include/asm/arch-sunxi/clock_sun50i_h6.h | 10 ++++++ > arch/arm/mach-sunxi/clock_sun50i_h6.c | 32 ++++++++++++++----- > 2 files changed, 34 insertions(+), 8 deletions(-) >=20 > diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm= /include/asm/arch-sunxi/clock_sun50i_h6.h > index c95f2b39e64..d251ed49798 100644 > --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h > +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h > @@ -101,6 +101,13 @@ > #define CCM_PLL6_DEFAULT 0xe8216300 > #define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000002 > #define CCM_APB1_DEFAULT 0x03000102 > + > +#elif CONFIG_MACH_SUN55I_A523 /* A523 */ > + > +#define CCM_PLL6_DEFAULT 0xe8116310 /* 1200 MHz */ > +#define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000002 /* 200 MHz */ > +#define CCM_APB1_DEFAULT 0x03000005 /* APB0 really */ > +#define CCM_APB2_DEFAULT 0x03000005 /* APB1 really */ > #endif > =20 > /* apb2 bit field */ > @@ -120,6 +127,7 @@ > /* MBUS clock bit field */ > #define MBUS_ENABLE BIT(31) > #define MBUS_RESET BIT(30) > +#define MBUS_UPDATE BIT(27) > #define MBUS_CLK_SRC_MASK GENMASK(25, 24) > #define MBUS_CLK_SRC_OSCM24 (0 << 24) > #define MBUS_CLK_SRC_PLL6X2 (1 << 24) > @@ -132,10 +140,12 @@ > #define GATE_SHIFT (0) > =20 > /* DRAM clock bit field */ > +#define DRAM_CLK_ENABLE BIT(31) > #define DRAM_MOD_RESET BIT(30) > #define DRAM_CLK_UPDATE BIT(27) > #define DRAM_CLK_SRC_MASK GENMASK(25, 24) > #define DRAM_CLK_SRC_PLL5 (0 << 24) > +#define DRAM_CLK_M_MASK (0x1f) > #define DRAM_CLK_M(m) (((m)-1) << 0) > =20 > /* MMC clock bit field */ > diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/= clock_sun50i_h6.c > index f76d1b83883..2ba144a6ac3 100644 > --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c > +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c > @@ -14,15 +14,22 @@ void clock_init_safe(void) > void *const ccm =3D (void *)SUNXI_CCM_BASE; > void *const prcm =3D (void *)SUNXI_PRCM_BASE; > =20 > - if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) { > - /* this seems to enable PLLs on H616 */ > + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) > setbits_le32(prcm + CCU_PRCM_SYS_PWROFF_GATING, 0x10); > + if (IS_ENABLED(CONFIG_MACH_SUN55I_A523)) > + setbits_le32(prcm + CCU_PRCM_SYS_PWROFF_GATING, 0x200); > + udelay(1); > + > + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || > + IS_ENABLED(CONFIG_MACH_SUN55I_A523)) > setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, 2); > - } > + udelay(1); > =20 > if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || > - IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { > + IS_ENABLED(CONFIG_MACH_SUN50I_H6) || > + IS_ENABLED(CONFIG_MACH_SUN55I_A523)) { > clrbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, 1); > + udelay(1); > setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, 1); > } > =20 > @@ -39,9 +46,10 @@ void clock_init_safe(void) > while (!(readl(ccm + CCU_H6_PLL6_CFG) & CCM_PLL_LOCK)) > ; > =20 > - clrsetbits_le32(ccm + CCU_H6_CPU_AXI_CFG, > - CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK, > - CCM_CPU_AXI_DEFAULT_FACTORS); > + if (!IS_ENABLED(CONFIG_MACH_SUN55I_A523)) > + clrsetbits_le32(ccm + CCU_H6_CPU_AXI_CFG, > + CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK, > + CCM_CPU_AXI_DEFAULT_FACTORS); > =20 > writel(CCM_PSI_AHB1_AHB2_DEFAULT, ccm + CCU_H6_PSI_AHB1_AHB2_CFG); > #ifdef CCM_AHB3_DEFAULT > @@ -53,7 +61,15 @@ void clock_init_safe(void) > * The mux and factor are set, but the clock will be enabled in > * DRAM initialization code. > */ > - writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), ccm + CCU_H6_MBUS_CFG); > + if (IS_ENABLED(CONFIG_MACH_SUN55I_A523)) { > + writel(MBUS_RESET, ccm + CCU_H6_MBUS_CFG); > + udelay(1); > + writel(MBUS_UPDATE | MBUS_CLK_SRC_OSCM24 | MBUS_CLK_M(4), > + ccm + CCU_H6_MBUS_CFG); > + } else { > + writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), > + ccm + CCU_H6_MBUS_CFG); > + } While this is in BSP boot0, I don't think it's needed at all. Full reset is done later in DRAM driver anyway. Best regards, Jernej > } > =20 > void clock_init_uart(void) >=20