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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43aba5710ebsm238381775e9.26.2025.03.04.07.28.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 07:28:50 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland , Andre Przywara Cc: Philipp Zabel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 03/15] clk: sunxi-ng: Add support for update bit Date: Tue, 04 Mar 2025 16:28:48 +0100 Message-ID: <3616088.iIbC2pHGDl@jernej-laptop> In-Reply-To: <20250304012805.28594-4-andre.przywara@arm.com> References: <20250304012805.28594-1-andre.przywara@arm.com> <20250304012805.28594-4-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne torek, 4. marec 2025 ob 02:27:53 Srednjeevropski standardni =C4=8Das je= Andre Przywara napisal(a): > Some clocks in the Allwinner A523 SoC contain an "update bit" (bit 27), > which must be set to apply any register changes, namely the mux > selector, the divider and the gate bit. >=20 > Add a new CCU feature bit to mark those clocks, and set bit 27 whenever > we are applying any changes. >=20 > Signed-off-by: Andre Przywara > --- > drivers/clk/sunxi-ng/ccu_common.h | 4 ++++ > drivers/clk/sunxi-ng/ccu_div.c | 2 ++ > drivers/clk/sunxi-ng/ccu_gate.c | 4 ++++ > drivers/clk/sunxi-ng/ccu_mux.c | 2 ++ > 4 files changed, 12 insertions(+) >=20 > diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu= _common.h > index 50fd268329671..d41d33bdff470 100644 > --- a/drivers/clk/sunxi-ng/ccu_common.h > +++ b/drivers/clk/sunxi-ng/ccu_common.h > @@ -20,10 +20,14 @@ > #define CCU_FEATURE_KEY_FIELD BIT(8) > #define CCU_FEATURE_CLOSEST_RATE BIT(9) > #define CCU_FEATURE_DUAL_DIV BIT(10) > +#define CCU_FEATURE_UPDATE_BIT27 BIT(11) There is no reason to have "BIT27" in the name of the macro. This is similar to KEY_FIELD, which is generic name and doesn't specify either key or posit= ion of this key field. Maybe just CCU_FEATURE_UPDATE_BIT or something equaly generic. With that fixed: Reviewed-by: Jernej Skrabec Best regards, Jernej > =20 > /* MMC timing mode switch bit */ > #define CCU_MMC_NEW_TIMING_MODE BIT(30) > =20 > +/* Some clocks need this bit to actually apply register changes */ > +#define CCU_SUNXI_UPDATE_BIT BIT(27) > + > struct device_node; > =20 > struct ccu_common { > diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_di= v.c > index 7f4691f09e01f..2d8b98fe4b13a 100644 > --- a/drivers/clk/sunxi-ng/ccu_div.c > +++ b/drivers/clk/sunxi-ng/ccu_div.c > @@ -106,6 +106,8 @@ static int ccu_div_set_rate(struct clk_hw *hw, unsign= ed long rate, > =20 > reg =3D readl(cd->common.base + cd->common.reg); > reg &=3D ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift); > + if (cd->common.features & CCU_FEATURE_UPDATE_BIT27) > + reg |=3D CCU_SUNXI_UPDATE_BIT; > =20 > writel(reg | (val << cd->div.shift), > cd->common.base + cd->common.reg); > diff --git a/drivers/clk/sunxi-ng/ccu_gate.c b/drivers/clk/sunxi-ng/ccu_g= ate.c > index ac52fd6bff677..0490f95781361 100644 > --- a/drivers/clk/sunxi-ng/ccu_gate.c > +++ b/drivers/clk/sunxi-ng/ccu_gate.c > @@ -20,6 +20,8 @@ void ccu_gate_helper_disable(struct ccu_common *common,= u32 gate) > spin_lock_irqsave(common->lock, flags); > =20 > reg =3D readl(common->base + common->reg); > + if (common->features & CCU_FEATURE_UPDATE_BIT27) > + reg |=3D CCU_SUNXI_UPDATE_BIT; > writel(reg & ~gate, common->base + common->reg); > =20 > spin_unlock_irqrestore(common->lock, flags); > @@ -44,6 +46,8 @@ int ccu_gate_helper_enable(struct ccu_common *common, u= 32 gate) > spin_lock_irqsave(common->lock, flags); > =20 > reg =3D readl(common->base + common->reg); > + if (common->features & CCU_FEATURE_UPDATE_BIT27) > + reg |=3D CCU_SUNXI_UPDATE_BIT; > writel(reg | gate, common->base + common->reg); > =20 > spin_unlock_irqrestore(common->lock, flags); > diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mu= x.c > index d7ffbdeee9e04..82ee21e0d3a68 100644 > --- a/drivers/clk/sunxi-ng/ccu_mux.c > +++ b/drivers/clk/sunxi-ng/ccu_mux.c > @@ -197,6 +197,8 @@ int ccu_mux_helper_set_parent(struct ccu_common *comm= on, > /* The key field always reads as zero. */ > if (common->features & CCU_FEATURE_KEY_FIELD) > reg |=3D CCU_MUX_KEY_VALUE; > + if (common->features & CCU_FEATURE_UPDATE_BIT27) > + reg |=3D CCU_SUNXI_UPDATE_BIT; > =20 > reg &=3D ~GENMASK(cm->width + cm->shift - 1, cm->shift); > writel(reg | (index << cm->shift), common->base + common->reg); >=20