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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-459e0e70218sm289411705e9.20.2025.08.11.09.31.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 09:31:30 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Andre Przywara Cc: u-boot@lists.denx.de, Tom Rini , Cody Eksal , Chris Morgan , linux-sunxi@lists.linux.dev Subject: Re: [PATCH 2/3] sunxi: spl: initialise timer before clocks Date: Mon, 11 Aug 2025 18:31:29 +0200 Message-ID: <3833295.MHq7AAxBmi@jernej-laptop> In-Reply-To: <20250811165225.2a01a93d@donnerap.manchester.arm.com> References: <20250801234918.19176-1-andre.przywara@arm.com> <3363499.aeNJFYEL58@jernej-laptop> <20250811165225.2a01a93d@donnerap.manchester.arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne ponedeljek, 11. avgust 2025 ob 17:52:25 Srednjeevropski poletni =C4=8Da= s je Andre Przywara napisal(a): > On Mon, 11 Aug 2025 17:34:47 +0200 > Jernej =C5=A0krabec wrote: >=20 > > Dne sobota, 2. avgust 2025 ob 01:49:17 Srednjeevropski poletni =C4=8Das= je Andre Przywara napisal(a): > > > Recent changes in the H6 clock code added delay() calls into the SPL = clock > > > setup routine, which requires the timers to work. When compiling for > > > AArch64, we are always using the Arm Generic Timer (aka. arch timer), > > > which does not require further setup, hence having an empty timer_ini= t() > > > routine. > > > However for 32-bit SoCs we use the Allwinner timers, which require so= me > > > setup routine, and hence we need timer_init() to be called before > > > clock_init(). > > >=20 > > > Swap the order of the two calls, to be more robust when compiling the= H6 > > > clock code for AArch32 or when using the Allwinner timers for whatever > > > reason. > > >=20 > > > Signed-off-by: Andre Przywara > > > --- > > > arch/arm/mach-sunxi/board.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > >=20 > > > diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c > > > index fb4837c2082..432b1c10f92 100644 > > > --- a/arch/arm/mach-sunxi/board.c > > > +++ b/arch/arm/mach-sunxi/board.c > > > @@ -476,8 +476,8 @@ void board_init_f(ulong dummy) > > > /* Enable non-secure access to some peripherals */ > > > tzpc_init(); > > > =20 > > > - clock_init(); > > > timer_init(); > > > + clock_init(); =20 > >=20 > > I contemplated similar change in past. It works fine for 64-bit archite= ctures, > > but I'm unsure for 32-bit. If you take a look at A83t clock code, it us= es > > sdelay() exactly because timer is not initialized at that time. > >=20 > > So, are you sure that this change has no unwanted side effects? >=20 > No, I am not ;-) > I was about to test this on some more boards. But I think with the > change in that direction, the only issue would be if the timer_init() code > relies on the clocks being set up already. And since timer_init() is only > *one* rather small function, just doing MMIO accesses, I think the risk is > quite low. As long as clock function doesn't need to enable bus or module clock, everything should be fine. Quick check didn't show any such code so it is probably safe to switch. Best regards, Jernej >=20 > Thanks for having a look anyway, I will report back how the test goes. >=20 > Cheers, > Andre >=20 > >=20 > > > gpio_init(); > > > =20 > > > spl_init(); > > > =20 > >=20 > >=20 > >=20 > >=20 >=20 >=20