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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id s7-20020a5d5107000000b0034c61e211a5sm6351271wrt.63.2024.04.28.09.21.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Apr 2024 09:21:29 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: linux-sunxi@lists.linux.dev, Dragan Simic Cc: wens@csie.org, samuel@sholland.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H6 Date: Sun, 28 Apr 2024 18:21:28 +0200 Message-ID: <5773383.DvuYhMxLoT@jernej-laptop> In-Reply-To: <49abb93000078c692c48c0a65ff677893909361a.1714304071.git.dsimic@manjaro.org> References: <6a772756c2c677dbdaaab4a2c71a358d8e4b27e9.1714304058.git.dsimic@manjaro.org> <49abb93000078c692c48c0a65ff677893909361a.1714304071.git.dsimic@manjaro.org> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="utf-8" Dne nedelja, 28. april 2024 ob 13:40:36 GMT +2 je Dragan Simic napisal(a): > Add missing cache information to the Allwinner H6 SoC dtsi, to allow > the userspace, which includes lscpu(1) that uses the virtual files provided > by the kernel under the /sys/devices/system/cpu directory, to display the > proper H6 cache information. > > Adding the cache information to the H6 SoC dtsi also makes the following > warning message in the kernel log go away: > > cacheinfo: Unable to detect cache hierarchy for CPU 0 > > The cache parameters for the H6 dtsi were obtained and partially derived > by hand from the cache size and layout specifications found in the following > datasheets and technical reference manuals: > > - Allwinner H6 V200 datasheet, version 1.1 > - ARM Cortex-A53 revision r0p3 TRM, version E > > For future reference, here's a brief summary of the documentation: > > - All caches employ the 64-byte cache line length > - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction > cache and 32 KB of L1 4-way, set-associative data cache > - The entire SoC has 512 KB of unified L2 16-way, set-associative cache > > Signed-off-by: Dragan Simic Reviewed-by: Jernej Skrabec Best regards, Jernej