Re: [PATCH v3 07/65] clk: at91: sckc: Add a determine_rate hook

Claudiu.Beznea
2023-05-18T07:38:30Z

On 04.04.2023 13:10, Maxime Ripard wrote:
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>
> The SAM9x5 slow clock implements a mux with a set_parent hook, but
> doesn't provide a determine_rate implementation.
>
> This is a bit odd, since set_parent() is there to, as its name implies,
> change the parent of a clock. However, the most likely candidate to
> trigger that parent change is a call to clk_set_rate(), with
> determine_rate() figuring out which parent is the best suited for a
> given rate.
>
> The other trigger would be a call to clk_set_parent(), but it's far less
> used, and it doesn't look like there's any obvious user for that clock.
>
> So, the set_parent hook is effectively unused, possibly because of an
> oversight. However, it could also be an explicit decision by the
> original author to avoid any reparenting but through an explicit call to
> clk_set_parent().
>
> The latter case would be equivalent to setting the flag
> CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook
> to __clk_mux_determine_rate(). Indeed, if no determine_rate
> implementation is provided, clk_round_rate() (through
> clk_core_round_rate_nolock()) will call itself on the parent if
> CLK_SET_RATE_PARENT is set, and will not change the clock rate
> otherwise. __clk_mux_determine_rate() has the exact same behavior when
> CLK_SET_RATE_NO_REPARENT is set.
>
> And if it was an oversight, then we are at least explicit about our
> behavior now and it can be further refined down the line.
>
> Signed-off-by: Maxime Ripard <maxime@cerno.tech>

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>

Tested-by: Claudiu Beznea <claudiu.beznea@microchip.com>

> ---
> drivers/clk/at91/sckc.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
> index fdc9b669f8a7..9c42961a8a2f 100644
> --- a/drivers/clk/at91/sckc.c
> +++ b/drivers/clk/at91/sckc.c
> @@ -310,6 +310,7 @@ static u8 clk_sam9x5_slow_get_parent(struct clk_hw *hw)
> }
>
> static const struct clk_ops sam9x5_slow_ops = {
> + .determine_rate = __clk_mux_determine_rate,
> .set_parent = clk_sam9x5_slow_set_parent,
> .get_parent = clk_sam9x5_slow_get_parent,
> };
> @@ -337,7 +338,7 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr,
> init.ops = &sam9x5_slow_ops;
> init.parent_names = parent_names;
> init.num_parents = num_parents;
> - init.flags = 0;
> + init.flags = CLK_SET_RATE_NO_REPARENT;
>
> slowck->hw.init = &init;
> slowck->sckcr = sckcr;
>
> --
> 2.39.2
>