From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C258C7499 for ; Tue, 21 Jun 2022 21:06:20 +0000 (UTC) Received: by mail-wr1-f51.google.com with SMTP id n1so20381420wrg.12 for ; Tue, 21 Jun 2022 14:06:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=references:from:to:cc:subject:in-reply-to:date:message-id :mime-version; bh=B+AifBFHSjsojzLa/Un/BRuE3LfBPqi3dOTl8DfRwag=; b=jUd5EpK/oDVgY0PrmyIj4MbqMNgKMDJSXTdrkx7aDI+kKFIwzflLFxbl8tnmBcS4Tp gB4gaM7Xma3+XSg+VGLSGTTgAuKWgIh6oZEa3B1gj7CGcxjYDaT+mvOLqiK71CJ9lCAf VLJs+n52lPXvDYIMyuayGTeKnVXRXd+7SYpLLXlfBBqdyIzNsIzgV1Pov6IBTxeWpOLA y2WofGIr0wPjngMAcYFM5cXxiNo4M8n8MEvUAduAxgAsmqhRyoZLMLWAdXvCTVIIBRWG Zr/aISNe4jZxXrKY34Xe5QxN9wI5wZzSkhMqFa50UXd8ZPYof9DpGUqyIGw0r9T09fDC iUAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:references:from:to:cc:subject:in-reply-to:date :message-id:mime-version; bh=B+AifBFHSjsojzLa/Un/BRuE3LfBPqi3dOTl8DfRwag=; b=WwLO22+bULNTr5y83Ukv+ftO5h5VQCJf2Xmzj8nRWoGv13T2sf/PI1g1XyQpgja0/l wCqpZGl7EpvQUSBV55KNFTkDV2TD8B2wHYy9YB5vjsy9UpT6gThIMDcM50JQri86SX8Z uwDzEhi4LMHrThSpXes+UJmM0AvmYgBrgx/y3AJgGdtFn8ZosBu4eHGHbTpBqWd9Zlc0 kfcg6aRLlPSTvhgLe9JR6fHDQXCd1rxujdrJCvhO7VurqsvgYXk39iCjYiFWcA+O759q k5sbzDu74D+RSIvUDOpmYVO7+jbAddalE6Dza+lY1w4bLow9vMMdaZFgkbKtk1nLoj0Q kaXw== X-Gm-Message-State: AJIora+as8vUrBOX4EpFuK8gmhZxlkTEaPKtK+cl4WQ2OSXRqz6S1Wwy KdMQoMPyq6wWzTkNy5tY9kA= X-Google-Smtp-Source: AGRyM1ts9ak9btzFswFUFoMElfPqueKySjcD1ty3sVAYSJ8wBUDzoTa0DLvFqOB9/wbjCt3Z3zA1LA== X-Received: by 2002:a5d:47a5:0:b0:210:2b96:a952 with SMTP id 5-20020a5d47a5000000b002102b96a952mr31343094wrb.248.1655845578965; Tue, 21 Jun 2022 14:06:18 -0700 (PDT) Received: from localhost (92.40.168.124.threembb.co.uk. [92.40.168.124]) by smtp.gmail.com with ESMTPSA id j1-20020adfff81000000b00210bac248c8sm16976883wrr.11.2022.06.21.14.06.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jun 2022 14:06:18 -0700 (PDT) References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> <20220620200644.1961936-18-aidanmacdonald.0x0@gmail.com> From: Aidan MacDonald To: Andy Shevchenko Cc: Mark Brown , Andy Gross , Bjorn Andersson , Srinivas Kandagatla , Banajit Goswami , Greg Kroah-Hartman , "Rafael J. Wysocki" , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , MyungJoo Ham , Michael Walle , Linus Walleij , Bartosz Golaszewski , Thomas Gleixner , Marc Zyngier , Lee Jones , Manivannan Sadhasivam , Cristian Ciocaltea , Chen-Yu Tsai , tharvey@gateworks.com, rjones@gateworks.com, Matti Vaittinen , orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, Jernej Skrabec , Samuel Holland , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Linux Kernel Mailing List , "open list:GPIO SUBSYSTEM" , linux-actions@lists.infradead.org, linux-arm-msm , linux-arm Mailing List , linux-sunxi@lists.linux.dev, ALSA Development Mailing List Subject: Re: [PATCH 17/49] regmap-irq: Add broken_mask_unmask flag In-reply-to: Date: Tue, 21 Jun 2022 22:07:24 +0100 Message-ID: <6DVb6JaRd4bhUPBIyfXXiqm668jAPyls@localhost> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain Andy Shevchenko writes: > On Mon, Jun 20, 2022 at 10:08 PM Aidan MacDonald > wrote: >> >> This flag is necessary to prepare for fixing the behavior of unmask >> registers. Existing chips that set mask_base and unmask_base must >> set broken_mask_unmask=1 to declare that they expect the mask bits > > Boolean should take true/false. > >> will be inverted in both registers, contrary to the usual behavior >> of mask registers. > >> diff --git a/include/linux/regmap.h b/include/linux/regmap.h >> index ee2567a0465c..21a70fd99493 100644 >> --- a/include/linux/regmap.h >> +++ b/include/linux/regmap.h >> @@ -1523,6 +1523,7 @@ struct regmap_irq_chip { >> bool clear_on_unmask:1; >> bool not_fixed_stride:1; >> bool status_invert:1; >> + bool broken_mask_unmask:1; > > Looking at the given context, I would group it with clean_on_unmask above. > > The above is weird enough on its own. Can you prepare a precursor > patch that either drops the bit fields of booleans or moves them to > unsigned int? Sure. > Note, bit fields in C are beasts when it goes to concurrent access. It > would be nice to ensure these are not the cases of a such. These are read-only so there's no danger here.