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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4409d2d868asm31066455e9.26.2025.04.24.12.21.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Apr 2025 12:21:10 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Andrew Lunn , wens@csie.org Cc: Andre Przywara , Yixun Lan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Samuel Holland , Maxime Ripard , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, clabbe.montjoie@gmail.com Subject: Re: [PATCH 4/5] arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E board Date: Thu, 24 Apr 2025 21:21:09 +0200 Message-ID: <8516361.T7Z3S40VBb@jernej-laptop> In-Reply-To: References: <20250423-01-sun55i-emac0-v1-0-46ee4c855e0a@gentoo.org> <7fcedce7-5cfe-48a4-9769-e6e7e82dc786@lunn.ch> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne =C4=8Detrtek, 24. april 2025 ob 21:05:17 Srednjeevropski poletni =C4=8D= as je Chen-Yu Tsai napisal(a): > On Fri, Apr 25, 2025 at 3:02=E2=80=AFAM Andrew Lunn wrot= e: > > > > > In my experience, vendor DT has proper delays specified, just 7 inste= ad of > > > 700, for example. What they get wrong, or better said, don't care, is= phy > > > mode. It's always set to rgmii because phy driver most of the time ig= nores > > > this value and phy IC just uses mode set using resistors. Proper way = here > > > would be to check schematic and set phy mode according to that. This = method > > > always works, except for one board, which had resistors set wrong and > > > phy mode configured over phy driver was actually fix for it. > > > > What PHY driver is this? If it is ignoring the mode, it is broken. > > > > We have had problems in the past in this respect. A PHY driver which > > ignored the RGMII modes, and strapping was used. That 'worked' until > > somebody built a board with broken strapping and added code to respect > > the RGMII mode, overriding the strapping. It made that board work, but > > broke lots of others which had the wrong RGMII mode.... > > > > If we have this again, i would like to know so we can try to get in > > front of the problem, before we have lots of broken boards... >=20 > I think the incident you are referring to is exactly the one that Jernej > mentioned. >=20 > And regarding the bad PHY driver, it could simply be that the PHY driver > was not built or not loaded, hence the kernel falling back to the generic > one, which of course doesn't know how to set the modes. Mainline is sorted out as far as I'm aware. Broken PHY drivers are part of BSP code drops, from where these values are taken from. So, for sure I wouldn't trust phy mode set in BSP code, but allwinner,tx-delay-ps and allwinner,rx-delay-ps are usually trustworthy. Best regards, Jernej