From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from relay06.th.seeweb.it (relay06.th.seeweb.it [5.144.164.167]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC170C8E4 for ; Mon, 4 Sep 2023 19:52:30 +0000 (UTC) Received: from [192.168.2.144] (bband-dyn191.178-41-225.t-com.sk [178.41.225.191]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 77A3F3E8E9; Mon, 4 Sep 2023 21:52:26 +0200 (CEST) Date: Mon, 04 Sep 2023 21:52:20 +0200 From: Martin Botka Subject: Re: [PATCH 3/6] dt-bindings: opp: Add compatible for H616 To: Krzysztof Kozlowski Cc: Mark Rutland , Lorenzo Pieralisi , Sudeep Holla , "Rafael J. Wysocki" , Viresh Kumar , Yangtao Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, Andre Przywara , Alan Ma , Luke Harrison , Marijn Suijten , AngeloGioacchino Del Regno , Konrad Dybcio , Rogerio Goncalves , Martin Botka Message-Id: <8J8H0S.3S79WVSTQOC92@somainline.org> In-Reply-To: References: <20230904-cpufreq-h616-v1-0-b8842e525c43@somainline.org> <20230904-cpufreq-h616-v1-3-b8842e525c43@somainline.org> X-Mailer: geary/43.0 Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed On Mon, Sep 4 2023 at 09:31:34 PM +02:00:00, Krzysztof Kozlowski wrote: > On 04/09/2023 17:57, Martin Botka wrote: >> We need to add compatible for H616 to H6 cpufreq driver bindings. > > Please describe the hardware, not what is needed for drivers. Got it. Sorry. > >> >> Also enable opp_supported_hw property that will be needed for H616. >> >> Signed-off-by: Martin Botka >> --- >> .../bindings/opp/allwinner,sun50i-h6-operating-points.yaml >> | 6 +++++- >> 1 file changed, 5 insertions(+), 1 deletion(-) >> >> diff --git >> a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml >> b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml >> index 51f62c3ae194..2fa1199f2d23 100644 >> --- >> a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml >> +++ >> b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml >> @@ -23,7 +23,10 @@ allOf: >> >> properties: >> compatible: >> - const: allwinner,sun50i-h6-operating-points >> + contains: > > This does not look like part of allOf, so contains is no correct here. > This must be specific, so drop contains. ack. > >> + enum: >> + - allwinner,sun50i-h6-operating-points >> + - allwinner,sun50i-h616-operating-points >> >> nvmem-cells: >> description: | >> @@ -47,6 +50,7 @@ patternProperties: >> properties: >> opp-hz: true >> clock-latency-ns: true >> + opp-supported-hw: true > > Why? It is already allowed. You should rather explain the values. Yea this can be dropped. I forgot to remove it. My bad. Also the values i think are very clear ? The values converted to binary represent which chip revision is allowed to use the specified frequency. 1 bit for each revision. > >> > > Best regards, > Krzysztof >