From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CAF11482F2; Sat, 8 Nov 2025 14:48:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762613306; cv=none; b=anPAjDys8pMm/LEbRhzUCE9A0ZLr3JSZOEdRkvgLYmuOS5tmqejOlkhzrgzzQZHkGPCryUb1AYVsNZztK1OC4vPGADDRQTNLZMvNiiRB9W1Ezumf4E/OqK3iEJj1V0ea8qRo0SoVj0RrFr58+0BoCYrEpWtUJeCL88odTI0AtDU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762613306; c=relaxed/simple; bh=Oo6g0GMqZZTxcLBaU6ktO2ZbYIHNWh6xms/osvI8ZXk=; h=Message-ID:Date:MIME-Version:Subject:From:To:Cc:References: In-Reply-To:Content-Type; b=Wz1nGLqnrORvhwFVcJd6EpjertgQ+nWm4Ghg4aXVAN3zrrco+XfvCZ2p4UjKRV5s0FLw4qP67nSHiqJCqoQRUhNZSsEG2p48gTFm3038i4J7bkV/34C6PCEjxUNiCEndFpyAbbguaz8Hss8I4IYrR/amhbQC1+Sjqmt0b66hFf8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=p4MMhFNg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="p4MMhFNg" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3B07CC116C6; Sat, 8 Nov 2025 14:48:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762613305; bh=Oo6g0GMqZZTxcLBaU6ktO2ZbYIHNWh6xms/osvI8ZXk=; h=Date:Subject:From:To:Cc:References:In-Reply-To:From; b=p4MMhFNgIiEyu6JE5Sc+kBWEcofVF4L9uJDCtmLTbYMG+XZf/cxIwjGxpAnOpJCsP EB7vV4c1DKZL1kQJrxFX9GRiyCsO/w0QP/cUEmADttS+uOUEpVDziA64e0XrKxe1GL 7ex1Q/pVH7TO7Gl15DeWbkfqOqcB+efTWhzxksys/R1bFufrXuhgq4EEx1MrdzdrmV jtzipSeOA5BSkFmP1O1Neud1d4jrjDqbQAs+DivvbSRh0ZzlhLxgcV6xvID/LWhGUo H507ZFLIxGZ9eBNUQYhws8KI/+07kQoWebBf4wUkHYs4BxSM37fFErYg2LJ9B8710y Aya/LGR/5d4MA== Message-ID: <8ae5d81d-4869-4c39-9561-cb0f87da70fd@kernel.org> Date: Sat, 8 Nov 2025 15:48:18 +0100 Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu From: Krzysztof Kozlowski To: revy Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Rob Herring , krzk+dt@kernel.org, conor+dt@kernel.org, Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Yixun Lan , Drew Fustini , geert+renesas@glider.be, Guodong Xu , Haylen Chu , Joel Stanley , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Han Gao References: <43109A90-8447-4006-8E29-2D2C0866758F@iscas.ac.cn> <287444fa-120c-42b4-9919-2f05ab1a2ab7@kernel.org> Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 08/11/2025 15:47, Krzysztof Kozlowski wrote: > On 08/11/2025 14:59, revy wrote: >> >> >> >>> -----Original Messages----- >>> From: "Krzysztof Kozlowski" >>> Sent Time: 2025-11-08 19:29:07 (Saturday) >>> To: gaohan@iscas.ac.cn, "Paul Walmsley" , "Palmer Dabbelt" , "Albert Ou" , "Alexandre Ghiti" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Chen-Yu Tsai" , "Jernej Skrabec" , "Samuel Holland" , "Yixun Lan" , "Drew Fustini" , "Geert Uytterhoeven" , "Guodong Xu" , "Haylen Chu" , "Joel Stanley" >>> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, "Han Gao" >>> Subject: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu >>> >>> On 08/11/2025 09:20, gaohan@iscas.ac.cn wrote: >>>> From: Han Gao >>>> >>>> Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V, >>>> using different IPs. >>>> >>>> d1(s): Xuantie C906 >>>> v821: Andes A27 + XuanTie E907 >>>> v861/v881: XuanTie C907 >>>> >>>> Signed-off-by: Han Gao >>>> --- >>>> arch/riscv/Kconfig.socs | 22 +++++++++++++++++----- >>>> 1 file changed, 17 insertions(+), 5 deletions(-) >>>> >>>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs >>>> index 848e7149e443..7cba5d6ec4c3 100644 >>>> --- a/arch/riscv/Kconfig.socs >>>> +++ b/arch/riscv/Kconfig.socs >>>> @@ -54,14 +54,26 @@ config SOC_STARFIVE >>>> help >>>> This enables support for StarFive SoC platform hardware. >>>> >>>> -config ARCH_SUNXI >>>> - bool "Allwinner sun20i SoCs" >>>> +menuconfig ARCH_SUNXI >>>> + bool "Allwinner RISC-V SoCs" >>>> + >>>> +if ARCH_SUNXI >>>> + >>>> +config ARCH_SUNXI_XUANTIE >>> >>> >>> You should not get multiple ARCHs. ARCH is only one. There is also not >>> much rationale in commit msg for that. >> >> The main goal is to avoid choosing multiple IP addresses for erreta. >> If using Andes IPs, I don't want to choose XuanTIe (T-Head) ERRETA. > > Not explained in commit msg but anyway not a good argument. It is some > sort of micro optimization and you completely miss the point we target > multiarch kernels. Heh, and I actually did not forbid or discourage choosing erratas per your soc. I said you only get one top level ARCH. Look at all arm64 platforms. How many ARCHs are there per one vendor? Best regards, Krzysztof