From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ot1-f45.google.com (mail-ot1-f45.google.com [209.85.210.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C5EF4A8F for ; Tue, 8 Mar 2022 16:10:26 +0000 (UTC) Received: by mail-ot1-f45.google.com with SMTP id t8-20020a0568301e2800b005b235a56f2dso4761989otr.9 for ; Tue, 08 Mar 2022 08:10:26 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=KyPMfupEleyChJaoF32kD8RM8iDdBNnSag4/WPn+wSg=; b=QRgJSNA+bnUfi7AwhuAL8GOSNjqmWMw+Em4xgsnXdIR92WH2Ym9GB/gZeoPhZ3VuRE 1EJWw+xZy3vBAjfvMNsvtW1dn/k02ogLZNAgyeBkj/BF3weQljpCHvy7AorCcF3QDbIg o+zk0rZcqDEjG87RAAPy38d8ILhjP9DMgRFvXvU/xQcRKYExsAyJEhdPSxbCpIDo6pmd BE9wo3Jxn3xr/T09LZhjRgbPSoym5z+x5zOQHA4roOSVccQzeAlIGD7VLHDODKejG1y9 kzshmnXLZTYLYIUPXptRcoajAGo3aRmIbg3mbefzD65zbjDex1pYvOZoKjC0x6IQlD6w OR5w== X-Gm-Message-State: AOAM533ndXLpngAPeP6bfA40l1LBhk640z/sixRWTvSpcLFaPFw/xBfs MTRlXGBCkvyzLsXVa3Dsag== X-Google-Smtp-Source: ABdhPJyXTiJ+e/GeI6w1oVwRWDTza1x93/zx+7ZIjP9/OFj7HfNrCrfoNhNES3iqqkqU+ttk3AmrXg== X-Received: by 2002:a9d:20ca:0:b0:5ad:3241:47f0 with SMTP id x68-20020a9d20ca000000b005ad324147f0mr8737395ota.269.1646755825679; Tue, 08 Mar 2022 08:10:25 -0800 (PST) Received: from robh.at.kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id f10-20020a4a8f4a000000b00320e5ecfecdsm2957842ool.46.2022.03.08.08.10.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 08:10:24 -0800 (PST) Received: (nullmailer pid 850672 invoked by uid 1000); Tue, 08 Mar 2022 16:10:23 -0000 Date: Tue, 8 Mar 2022 10:10:23 -0600 From: Rob Herring To: Andre Przywara Cc: Samuel Holland , Jernej Skrabec , linux-sunxi@lists.linux.dev, Maxime Ripard , Giulio Benetti , Ulf Hansson , Rob Herring , Chen-Yu Tsai , Icenowy Zheng , linux-arm-kernel@lists.infradead.org, Jesse Taube , linux-mmc@vger.kernel.org, George Hilliard , devicetree@vger.kernel.org, Mesih Kilinc Subject: Re: [PATCH 07/14] dt-bindings: mmc: sunxi: add Allwinner F1c100s compatible Message-ID: References: <20220307143421.1106209-1-andre.przywara@arm.com> <20220307143421.1106209-8-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220307143421.1106209-8-andre.przywara@arm.com> On Mon, 07 Mar 2022 14:34:14 +0000, Andre Przywara wrote: > From: Jesse Taube > > The Allwinner F1C100 series contains two MMC controller blocks. From > comparing the data sheets, they seem to be compatible with the one used > in the Allwinner A20: the register layout is the same, and they use the > same separate sample and output clocks design. > The only difference is the missing reset line in the A20 version, but > both the binding and the Linux driver make this optional, so it's still > a fit. > > Add the new SoC specific name and require it to be paired with the A20 > fallback name, as this is all the driver needs to care about. > > Signed-off-by: Jesse Taube > Signed-off-by: Andre Przywara > --- > .../devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 3 +++ > 1 file changed, 3 insertions(+) > Acked-by: Rob Herring