From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F2571607BD for ; Wed, 1 May 2024 19:31:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714591881; cv=none; b=qatol+DO0IB3EHE6rk0SNPNuu9l4DByYX3vEnySi5iN50bIccE7vOt2/R+u5GkN1pzLeYEfPvfDJUUoRTj85H5+D3CFjbo/a3NHBC0EzHDdx+1aHUiVBul5+Y3M51OGIRzx33HLsE+VG93NfxZvsBVhjR/yH7Ul4DAaj/6LCK9w= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714591881; c=relaxed/simple; bh=4V4nOXAJK4lEKU8JJiUWuMjaMfSMrqSP/Y1lsJzv9Ms=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=G2I8f2ErNJpxrdenRZ/V19W4Y41t4oHK7+/maS63/g6GtKoWcaT68Y6khzD+5LFnECEXFunzPcoNwtW2XQlg/RaJkwGdBvcgOVKpMPEPvecPtbA+P/DASPxPblOuHuxDCiEDM0v6HPlfsm1wFfxh/+TvVuG0GcKbLVxjtTj0aVY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=Yc+ExzOM; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="Yc+ExzOM" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-1ec5387aed9so17746115ad.3 for ; Wed, 01 May 2024 12:31:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1714591879; x=1715196679; darn=lists.linux.dev; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=yCUZ0lJZi4XrPs9F0orCitlVzShTGN4BIsUI0TAYPxE=; b=Yc+ExzOMq5be1xGoaHpYMB0gU/Yfj9wVZyNlAo9RxMQPlsUgpnGUTgOtWKejurdp+h iIjAvqAxhZWEGaNlSc7FnZB7AaZ16NfyCx0Rj26pFi3cuk23EsejvvemUit805LTdjDX ylpQ63Rd7tIcvXff2EJ/UJtcWeaEIo9ZVd6a095MUn+ZoCyRAsx5BubpxEADiLbD0hDg aCwkt1UHaUJJ9iQPXGiBbmO72CO2MrNMSzWNmrh6vrZemvbOSnTGDzoO/p7noLi2dGry HXfts3V/3pBoGeQJZ+PdvukkFxeOsnc7UcP1wyo2BjEO7RZdP8bVkuLi1Uevx3bmhxsN b5tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714591879; x=1715196679; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=yCUZ0lJZi4XrPs9F0orCitlVzShTGN4BIsUI0TAYPxE=; b=qV8R3uTxlolmxAjfZUU0I0Kpgqq1BeLXUalHYU8w+ZPUfybwi2BIbfeabWKmMPgIBU mS6A8DEnZR33RzQssphSBdekn0U4g14Y7Yk9YBYek1klA6q+aUEk3kQnmL2qo0oreg2d d1RasllZZNb+WyeLDeckuMUnMJ/JKgdq0lzxv/zRsewR7xeia+PMbmPf0ugEMz/9f9+W fh2vobrgxXb94ETMVdiKmW+lXx3pOWaTNTSceG/5rYHHpiSifq85mqn6jEyArZ81pPPF A8XC/vW2qtiv3otWRlB/uiWfnnYFc+2AwPS4DQWr2s/3CBMIiNA7JibRZShSghCb766R G4FQ== X-Forwarded-Encrypted: i=1; AJvYcCX3KlV0CAPDQPeJJy1UM3g1CYyJgqrwXws2mcAie6qj/MQBcJ2t7Uq0W2nbQoyWJD8P5Il6Zyu1kg9r6NEMqWRak49ujiHCZcyr9v4= X-Gm-Message-State: AOJu0YyIfGrmUnZjW7AfaXl00s4c0tLN78Q49/LnrEl2wiS9y/+to63e GkH0YTcizjf7EJ6aP4hnTXPO342jdBPkX7ZK21ISLubaanzoGf3TGgo9G0d0Bdw= X-Google-Smtp-Source: AGHT+IF+r6LzNom8uhqtQWXEjd5uhhgWb7qm6I7GST1rhNDBMa9dUd0xMpP2FPO8ekUjklgZmgxoeQ== X-Received: by 2002:a17:902:aa01:b0:1eb:49cb:bf70 with SMTP id be1-20020a170902aa0100b001eb49cbbf70mr3274061plb.62.1714591879439; Wed, 01 May 2024 12:31:19 -0700 (PDT) Received: from ghost ([2601:647:5700:6860:1dcc:e03e:dc61:895d]) by smtp.gmail.com with ESMTPSA id h4-20020a170902f7c400b001ec76a2303bsm2192009plw.175.2024.05.01.12.31.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 12:31:18 -0700 (PDT) Date: Wed, 1 May 2024 12:31:15 -0700 From: Charlie Jenkins To: Evan Green Cc: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Jonathan Corbet , Shuah Khan , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v4 13/16] riscv: hwprobe: Add thead vendor extension probing Message-ID: References: <20240426-dev-charlie-support_thead_vector_6_9-v4-0-5cf53b5bc492@rivosinc.com> <20240426-dev-charlie-support_thead_vector_6_9-v4-13-5cf53b5bc492@rivosinc.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Wed, May 01, 2024 at 09:46:00AM -0700, Evan Green wrote: > On Fri, Apr 26, 2024 at 2:37 PM Charlie Jenkins wrote: > > > > Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which > > allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR > > vendor extension. > > > > This new key will allow userspace code to probe for which thead vendor > > extensions are supported. This API is modeled to be consistent with > > RISCV_HWPROBE_KEY_IMA_EXT_0. The bitmask returned will have each bit > > corresponding to a supported thead vendor extension of the cpumask set. > > Just like RISCV_HWPROBE_KEY_IMA_EXT_0, this allows a userspace program > > to determine all of the supported thead vendor extensions in one call. > > > > Signed-off-by: Charlie Jenkins > > --- > > arch/riscv/include/asm/hwprobe.h | 4 +-- > > .../include/asm/vendor_extensions/thead_hwprobe.h | 11 ++++++ > > arch/riscv/include/uapi/asm/hwprobe.h | 3 +- > > arch/riscv/include/uapi/asm/vendor/thead.h | 3 ++ > > arch/riscv/kernel/sys_hwprobe.c | 9 +++++ > > arch/riscv/kernel/vendor_extensions/Makefile | 1 + > > .../riscv/kernel/vendor_extensions/thead_hwprobe.c | 42 ++++++++++++++++++++++ > > 7 files changed, 70 insertions(+), 3 deletions(-) > > > > diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h > > index 630507dff5ea..e68496b4f8de 100644 > > --- a/arch/riscv/include/asm/hwprobe.h > > +++ b/arch/riscv/include/asm/hwprobe.h > > @@ -1,6 +1,6 @@ > > /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > > /* > > - * Copyright 2023 Rivos, Inc > > + * Copyright 2023-2024 Rivos, Inc > > */ > > > > #ifndef _ASM_HWPROBE_H > > @@ -8,7 +8,7 @@ > > > > #include > > > > -#define RISCV_HWPROBE_MAX_KEY 6 > > +#define RISCV_HWPROBE_MAX_KEY 7 > > > > static inline bool riscv_hwprobe_key_is_valid(__s64 key) > > { > > diff --git a/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h b/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h > > new file mode 100644 > > index 000000000000..907cfc4eb4dc > > --- /dev/null > > +++ b/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h > > @@ -0,0 +1,11 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H > > +#define _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H > > + > > +#include > > + > > +#include > > + > > +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpumask *cpus); > > + > > +#endif > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > > index 9f2a8e3ff204..21e96a63f9ea 100644 > > --- a/arch/riscv/include/uapi/asm/hwprobe.h > > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > > @@ -1,6 +1,6 @@ > > /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > > /* > > - * Copyright 2023 Rivos, Inc > > + * Copyright 2023-2024 Rivos, Inc > > */ > > > > #ifndef _UAPI_ASM_HWPROBE_H > > @@ -67,6 +67,7 @@ struct riscv_hwprobe { > > #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) > > #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) > > #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 > > +#define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 7 > > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ > > > > /* Flags */ > > diff --git a/arch/riscv/include/uapi/asm/vendor/thead.h b/arch/riscv/include/uapi/asm/vendor/thead.h > > new file mode 100644 > > index 000000000000..43790ebe5faf > > --- /dev/null > > +++ b/arch/riscv/include/uapi/asm/vendor/thead.h > > @@ -0,0 +1,3 @@ > > +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > > + > > +#define RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR (1 << 0) > > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c > > index 8cae41a502dd..e59cac545df5 100644 > > --- a/arch/riscv/kernel/sys_hwprobe.c > > +++ b/arch/riscv/kernel/sys_hwprobe.c > > @@ -13,6 +13,7 @@ > > #include > > #include > > #include > > +#include > > #include > > > > > > @@ -216,6 +217,14 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > > pair->value = riscv_cboz_block_size; > > break; > > > > + case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: > > +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD > > + hwprobe_isa_vendor_ext_thead_0(pair, cpus); > > +#else > > + pair->value = 0; > > +#endif > > Could we move this ifdef into the header by declaring a dummy > hwprobe_isa_vendor_ext_thead_0() in the header for the !ENABLED case? > > > + break; > > + > > /* > > * For forward compatibility, unknown keys don't fail the whole > > * call, but get their element key set to -1 and value set to 0 > > diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile > > index 8f1c5a4dc38f..f511fd269e8a 100644 > > --- a/arch/riscv/kernel/vendor_extensions/Makefile > > +++ b/arch/riscv/kernel/vendor_extensions/Makefile > > @@ -1,4 +1,5 @@ > > # SPDX-License-Identifier: GPL-2.0-only > > > > obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead.o > > +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead_hwprobe.o > > obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) += andes.o > > diff --git a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c > > new file mode 100644 > > index 000000000000..e8e2de292032 > > --- /dev/null > > +++ b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c > > @@ -0,0 +1,42 @@ > > +// SPDX-License-Identifier: GPL-2.0-only > > + > > +#include > > +#include > > +#include > > + > > +#include > > +#include > > + > > +#include > > +#include > > + > > +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpumask *cpus) > > +{ > > + /* > > + * Loop through and record extensions that 1) anyone has, and 2) anyone > > + * doesn't have. > > + */ > > + > > + struct riscv_isainfo *per_hart_thead_bitmap = riscv_isa_vendor_ext_list_thead.per_hart_vendor_bitmap; > > + int cpu; > > + u64 missing; > > + > > + for_each_cpu(cpu, cpus) { > > + struct riscv_isainfo *isainfo = &per_hart_thead_bitmap[cpu]; > > + > > +#define EXT_KEY(ext) \ > > + do { \ > > + if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_VENDOR_EXT_##ext)) \ > > + pair->value |= RISCV_HWPROBE_VENDOR_EXT_##ext; \ > > + else \ > > + missing |= RISCV_HWPROBE_VENDOR_EXT_##ext; \ > > + } while (false) > > + > > + EXT_KEY(XTHEADVECTOR); > > + > > +#undef EXT_KEY > > + } > > + > > + /* Now turn off reporting features if any CPU is missing it. */> + pair->value &= ~missing; > > +} > > Something to consider, perhaps when there's a second vendor, is how we > might reduce this boilerplate on the second vendor. Probably best to > wait though until we know exactly what the commonalities are. This > looks good for now. > Yes it should be mostly identical on second vendor. I think the only difference would be "per_hart_thead_bitmap" and the list of extensions. I can probably factor this out a bit. - Charlie > > > > > -- > > 2.44.0 > >