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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <0944414F-321F-4159-AB85-C4B66AE9550B@jrtc27.com> On Mon, Jun 10, 2024 at 06:51:56PM +0100, Jessica Clarke wrote: > On 10 Jun 2024, at 05:45, Charlie Jenkins wrote: > > > > If thead,vlenb is provided in the device tree, prefer that over reading > > the vlenb csr. > > > > Signed-off-by: Charlie Jenkins > > --- > > arch/riscv/include/asm/cpufeature.h | 2 ++ > > arch/riscv/kernel/cpufeature.c | 48 +++++++++++++++++++++++++++++++++++++ > > arch/riscv/kernel/vector.c | 12 +++++++++- > > 3 files changed, 61 insertions(+), 1 deletion(-) > > > > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h > > index b029ca72cebc..e0a3164c7a06 100644 > > --- a/arch/riscv/include/asm/cpufeature.h > > +++ b/arch/riscv/include/asm/cpufeature.h > > @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); > > /* Per-cpu ISA extensions. */ > > extern struct riscv_isainfo hart_isa[NR_CPUS]; > > > > +extern u32 thead_vlenb_of; > > + > > void riscv_user_isa_enable(void); > > > > #define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) { \ > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index 2107c59575dd..0c01f33f2348 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -37,6 +37,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; > > /* Per-cpu ISA extensions. */ > > struct riscv_isainfo hart_isa[NR_CPUS]; > > > > +u32 thead_vlenb_of; > > + > > /** > > * riscv_isa_extension_base() - Get base extension word > > * > > @@ -625,6 +627,46 @@ static void __init riscv_fill_vendor_ext_list(int cpu) > > } > > } > > > > +static int has_thead_homogeneous_vlenb(void) > > +{ > > + int cpu; > > + u32 prev_vlenb = 0; > > + u32 vlenb; > > + > > + /* Ignore vlenb if vector is not enabled in the kernel */ > > + if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) > > It’s not V though. You probably want to split out “vector” from “V” in > Kconfig land. Most places want the former, I assume, but some want the > latter. There is the xtheadvector kconfig that is introduced later in this series in the "riscv: vector: Support xtheadvector save/restore" patch. I think I should shuffle the code in these patches around so I can use CONFIG_RISCV_ISA_XTHEADVECTOR here instead. - Charlie > > Jess > > > + return 0; > > + > > + for_each_possible_cpu(cpu) { > > + struct device_node *cpu_node; > > + > > + cpu_node = of_cpu_device_node_get(cpu); > > + if (!cpu_node) { > > + pr_warn("Unable to find cpu node\n"); > > + return -ENOENT; > > + } > > + > > + if (of_property_read_u32(cpu_node, "thead,vlenb", &vlenb)) { > > + of_node_put(cpu_node); > > + > > + if (prev_vlenb) > > + return -ENOENT; > > + continue; > > + } > > + > > + if (prev_vlenb && vlenb != prev_vlenb) { > > + of_node_put(cpu_node); > > + return -ENOENT; > > + } > > + > > + prev_vlenb = vlenb; > > + of_node_put(cpu_node); > > + } > > + > > + thead_vlenb_of = vlenb; > > + return 0; > > +} > > + > > static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) > > { > > unsigned int cpu; > > @@ -689,6 +731,12 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) > > riscv_fill_vendor_ext_list(cpu); > > } > > > > + if (riscv_isa_vendor_extension_available(THEAD_VENDOR_ID, XTHEADVECTOR) && > > + has_thead_homogeneous_vlenb() < 0) { > > + pr_warn("Unsupported heterogeneous vlenb detected, vector extension disabled.\n"); > > + elf_hwcap &= ~COMPAT_HWCAP_ISA_V; > > + } > > + > > if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) > > return -ENOENT; > > > > diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c > > index 6727d1d3b8f2..3ba2f2432483 100644 > > --- a/arch/riscv/kernel/vector.c > > +++ b/arch/riscv/kernel/vector.c > > @@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void) > > { > > unsigned long this_vsize; > > > > - /* There are 32 vector registers with vlenb length. */ > > + /* > > + * There are 32 vector registers with vlenb length. > > + * > > + * If the thead,vlenb property was provided by the firmware, use that > > + * instead of probing the CSRs. > > + */ > > + if (thead_vlenb_of) { > > + this_vsize = thead_vlenb_of * 32; > > + return 0; > > + } > > + > > riscv_v_enable(); > > this_vsize = csr_read(CSR_VLENB) * 32; > > riscv_v_disable(); > > > > -- > > 2.44.0 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv >