From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-188.mta0.migadu.com (out-188.mta0.migadu.com [91.218.175.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51CD11E87B for ; Fri, 8 Nov 2024 14:15:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.188 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731075352; cv=none; b=cUdDhNeHJ3Vdd5iFqaJRjzUbSkOWIKQ0YiUPAzvKBPpVoz3wabtCoycIGUFmI+QAgQL9Lb2NkFA54GJB2tm0YzE9tkJiVqtXTx1ptHTI3IYUZLf9RcoaoXLoM7ByBJrFHcvz6GmcSiFcGvh+5jy/rDJD5xrd5YK5Vd/TI1UIzO4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731075352; c=relaxed/simple; bh=ws+GTUComh8X1PZWMHIhgeWfmtmHHuB5QBXpYb87epw=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=UeTTPxmPmUMJW9E0dofR93He9PKS9abaSlxvKIJC9RB/ZmWa4VYl+0xD7cNpzpm4HE0XINSjnpiDbHiCNgPYOb+mfNor7Oy72QjJo0iQGL7bceLQIM+3G8qDC9wPiMSWsJ99qZ/6FYG5xHsac6wJx0rVhM1MZcOc1cboPSodfCQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=jookia.org; spf=pass smtp.mailfrom=jookia.org; dkim=pass (2048-bit key) header.d=jookia.org header.i=@jookia.org header.b=dyRNsVDT; arc=none smtp.client-ip=91.218.175.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=jookia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=jookia.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=jookia.org header.i=@jookia.org header.b="dyRNsVDT" Date: Sat, 9 Nov 2024 01:15:16 +1100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1731075347; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=LsPCVms6hNNfLUkJTitnYnu1jKozUMg34GhP2YbGR/Y=; b=dyRNsVDTwaKej4kfRQld0HktPA9K31WMR+7RMV7BkZyFHohDGsgh1Ni/SdHK1cF+2R1gR3 E44AMjR6bxQC7HScfiopeaR5sHe7tc5H73ez0wWQdpHXWy+DDSSuypMNYDuvBXu91X5OYX /zTcFle6IGlpjTeWpb1qWnbZ4sdt3OTUUJzLFXD85jv/Inx7Ng4nrf7Oa/tgwPYKYOHXfq q6Qyy6x94JDR5O6fGBJaN8B9vzCA5hihKqFw26GUNovZ5TwZAmuEy2myt3SLTCR/6xVmhU 05FqmKXjfPLpUsWxlc8ivY1X3kFTZyT6Tj9eDu6viVNU/iM4CR6BdagzgqLxEw== X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: John Watts To: Parthiban Cc: Andre Przywara , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Daniel Vetter , Samuel Holland , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH] drm/sun4i: Workaround TCON TOP conflict between DE0 and DE1 Message-ID: References: <20241108-tcon_fix-v1-1-616218cc0d5f@jookia.org> <20241108115357.691b77b0@donnerap.manchester.arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Migadu-Flow: FLOW_OUT On Fri, Nov 08, 2024 at 07:36:16PM +0530, Parthiban wrote: > To add, 0x20 will be DE0 <--> LCD0 and DE1 <--> TV0. Below note (copied from > R40) states the priority of the DE selection, which fails to work? Not sure, > may be disabling CORE1_SCLK_GATE and CORE1_HCLK_GATE in de2-clk helps. > > With A133 following the same as T113 with single mixer without TV, still > sets 0x20 in vendor kernel. > > copied from R40: > Note: The priority of DE0 is higher than DE1. > If TCON_LCD0 selects DE0 and DE1 as source at the same time, then > DE0 will be used for the source of TCON_LCD0. Hi there, Yes that was a pretty bad typo, I meant to say DE1 to TV0 The prioritization seems broken in the T113 at least, it's racy from what I see in testing. I should note this in the patch too. I looked at the datasheets and kernel code briefly: I can't seem to figure out what SCLK/HCLK gating does and I don't think the kernel touches these registers which are gated by default. > Thanks, > Parthiban John Watts