[PATCH net-next v9 6/6] net: stmmac: qcom-ethqos: add support for sa8255p

Bartosz Golaszewski
2026-03-16T12:05:54Z

Extend the driver to support a new model - sa8255p. Unlike the
previously supported variants, this one's power management is done in
the firmware using SCMI. This is modeled in linux using power domains so
add support for them.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
.../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 301 ++++++++++++++++++---
1 file changed, 262 insertions(+), 39 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index f32ff0d9ce513d8270c8db9c549a79778549df59..09ce80b446cbac8bf85d974a3d6517e037b049c1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -7,6 +7,8 @@
#include <linux/platform_device.h>
#include <linux/phy.h>
#include <linux/phy/phy.h>
+#include <linux/pm_opp.h>
+#include <linux/pm_domain.h>

#include "stmmac.h"
#include "stmmac_platform.h"
@@ -81,6 +83,13 @@

#define SGMII_10M_RX_CLK_DVDR 0x31

+enum ethqos_pd_selector {
+ ETHQOS_PD_CORE = 0,
+ ETHQOS_PD_MDIO,
+ ETHQOS_PD_SERDES,
+ ETHQOS_NUM_PDS,
+};
+
struct ethqos_emac_por {
unsigned int offset;
unsigned int value;
@@ -98,6 +107,9 @@ struct ethqos_emac_driver_data {

struct ethqos_emac_pm_data {
const char *link_clk_name;
+ bool use_domains;
+ struct dev_pm_domain_attach_data pd;
+ unsigned int clk_ptp_rate;
};

struct ethqos_emac_match_data {
@@ -110,13 +122,21 @@ struct ethqos_emac_pm_ctx {
struct phy *serdes_phy;
};

+struct ethqos_emac_pd_ctx {
+ struct dev_pm_domain_list *pd_list;
+ int serdes_level;
+};
+
struct qcom_ethqos {
struct platform_device *pdev;
void __iomem *rgmii_base;
void (*configure_func)(struct qcom_ethqos *ethqos,
phy_interface_t interface, int speed);

- struct ethqos_emac_pm_ctx pm;
+ union {
+ struct ethqos_emac_pm_ctx pm;
+ struct ethqos_emac_pd_ctx pd;
+ };
phy_interface_t phy_mode;

const struct ethqos_emac_por *rgmii_por;
@@ -338,6 +358,25 @@ static const struct ethqos_emac_match_data emac_sa8775p_data = {
.pm_data = &emac_sa8775p_pm_data,
};

+static const char * const emac_sa8255p_pd_names[] = {
+ "core", "mdio", "serdes"
+};
+
+static const struct ethqos_emac_pm_data emac_sa8255p_pm_data = {
+ .pd = {
+ .pd_flags = PD_FLAG_NO_DEV_LINK,
+ .pd_names = emac_sa8255p_pd_names,
+ .num_pd_names = ETHQOS_NUM_PDS,
+ },
+ .use_domains = true,
+ .clk_ptp_rate = 230400000,
+};
+
+static const struct ethqos_emac_match_data emac_sa8255p_data = {
+ .drv_data = &emac_v4_0_0_data,
+ .pm_data = &emac_sa8255p_pm_data,
+};
+
static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
{
struct device *dev = &ethqos->pdev->dev;
@@ -406,6 +445,28 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
return 0;
}

+static int qcom_ethqos_domain_on(struct qcom_ethqos *ethqos,
+ enum ethqos_pd_selector sel)
+{
+ struct device *dev = ethqos->pd.pd_list->pd_devs[sel];
+ int ret;
+
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret < 0)
+ dev_err(&ethqos->pdev->dev,
+ "Failed to enable the power domain for %s\n",
+ dev_name(dev));
+ return ret;
+}
+
+static void qcom_ethqos_domain_off(struct qcom_ethqos *ethqos,
+ enum ethqos_pd_selector sel)
+{
+ struct device *dev = ethqos->pd.pd_list->pd_devs[sel];
+
+ pm_runtime_put_sync(dev);
+}
+
static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
{
struct device *dev = &ethqos->pdev->dev;
@@ -655,6 +716,20 @@ static void ethqos_configure_sgmii(struct qcom_ethqos *ethqos,
ethqos_pcs_set_inband(priv, interface == PHY_INTERFACE_MODE_SGMII);
}

+static void ethqos_configure_sgmii_pd(struct qcom_ethqos *ethqos,
+ phy_interface_t interface, int speed)
+{
+ switch (speed) {
+ case SPEED_2500:
+ case SPEED_1000:
+ case SPEED_100:
+ case SPEED_10:
+ ethqos->pd.serdes_level = speed;
+ }
+
+ ethqos_configure_sgmii(ethqos, interface, speed);
+}
+
static void ethqos_configure(struct qcom_ethqos *ethqos,
phy_interface_t interface, int speed)
{
@@ -710,6 +785,45 @@ static int ethqos_mac_finish_serdes(struct net_device *ndev, void *priv,
return ret;
}

+static int ethqos_mac_finish_serdes_pd(struct net_device *ndev, void *priv,
+ unsigned int mode,
+ phy_interface_t interface)
+{
+ struct qcom_ethqos *ethqos = priv;
+ struct device *dev = ethqos->pd.pd_list->pd_devs[ETHQOS_PD_SERDES];
+ int ret = 0;
+
+ qcom_ethqos_set_sgmii_loopback(ethqos, false);
+
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_2500BASEX)
+ ret = dev_pm_opp_set_level(dev, ethqos->pd.serdes_level);
+
+ return ret;
+}
+
+static int qcom_ethqos_pd_serdes_powerup(struct net_device *ndev, void *priv)
+{
+ struct qcom_ethqos *ethqos = priv;
+ struct device *dev = ethqos->pd.pd_list->pd_devs[ETHQOS_PD_SERDES];
+ int ret;
+
+ ret = qcom_ethqos_domain_on(ethqos, ETHQOS_PD_SERDES);
+ if (ret < 0)
+ return ret;
+
+ return dev_pm_opp_set_level(dev, ethqos->pd.serdes_level);
+}
+
+static void qcom_ethqos_pd_serdes_powerdown(struct net_device *ndev, void *priv)
+{
+ struct qcom_ethqos *ethqos = priv;
+ struct device *dev = ethqos->pd.pd_list->pd_devs[ETHQOS_PD_SERDES];
+
+ dev_pm_opp_set_level(dev, 0);
+ qcom_ethqos_domain_off(ethqos, ETHQOS_PD_SERDES);
+}
+
static int ethqos_clks_config(void *priv, bool enabled)
{
struct qcom_ethqos *ethqos = priv;
@@ -741,6 +855,68 @@ static void ethqos_clks_disable(void *data)
ethqos_clks_config(data, false);
}

+static void ethqos_disable_serdes(void *data)
+{
+ struct qcom_ethqos *ethqos = data;
+
+ qcom_ethqos_domain_off(ethqos, ETHQOS_PD_SERDES);
+}
+
+static int ethqos_pd_clks_config(void *priv, bool enabled)
+{
+ struct qcom_ethqos *ethqos = priv;
+ int ret = 0;
+
+ if (enabled) {
+ ret = qcom_ethqos_domain_on(ethqos, ETHQOS_PD_MDIO);
+ if (ret < 0) {
+ dev_err(&ethqos->pdev->dev,
+ "Failed to enable the MDIO power domain\n");
+ return ret;
+ }
+
+ ethqos_set_func_clk_en(ethqos);
+ } else {
+ qcom_ethqos_domain_off(ethqos, ETHQOS_PD_MDIO);
+ }
+
+ return ret;
+}
+
+static int qcom_ethqos_pd_init(struct device *dev, void *priv)
+{
+ struct qcom_ethqos *ethqos = priv;
+ int ret;
+
+ /*
+ * Enable functional clock to prevent DMA reset after timeout due
+ * to no PHY clock being enabled after the hardware block has been
+ * power cycled. The actual configuration will be adjusted once
+ * ethqos_fix_mac_speed() is called.
+ */
+ ethqos_set_func_clk_en(ethqos);
+
+ ret = qcom_ethqos_domain_on(ethqos, ETHQOS_PD_CORE);
+ if (ret)
+ return ret;
+
+ ret = qcom_ethqos_domain_on(ethqos, ETHQOS_PD_MDIO);
+ if (ret) {
+ qcom_ethqos_domain_off(ethqos, ETHQOS_PD_CORE);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void qcom_ethqos_pd_exit(struct device *dev, void *data)
+{
+ struct qcom_ethqos *ethqos = data;
+
+ qcom_ethqos_domain_off(ethqos, ETHQOS_PD_MDIO);
+ qcom_ethqos_domain_off(ethqos, ETHQOS_PD_CORE);
+}
+
static void ethqos_ptp_clk_freq_config(struct stmmac_priv *priv)
{
struct plat_stmmacenet_data *plat_dat = priv->plat;
@@ -781,31 +957,11 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
"dt configuration failed\n");
}

- plat_dat->clks_config = ethqos_clks_config;
-
ethqos = devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL);
if (!ethqos)
return -ENOMEM;

ethqos->phy_mode = plat_dat->phy_interface;
- switch (ethqos->phy_mode) {
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- ethqos->configure_func = ethqos_configure_rgmii;
- break;
- case PHY_INTERFACE_MODE_2500BASEX:
- case PHY_INTERFACE_MODE_SGMII:
- ethqos->configure_func = ethqos_configure_sgmii;
- plat_dat->mac_finish = ethqos_mac_finish_serdes;
- break;
- default:
- dev_err(dev, "Unsupported phy mode %s\n",
- phy_modes(ethqos->phy_mode));
- return -EINVAL;
- }
-
ethqos->pdev = pdev;
ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii");
if (IS_ERR(ethqos->rgmii_base))
@@ -823,35 +979,101 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
ethqos->has_emac_ge_3 = drv_data->has_emac_ge_3;
ethqos->needs_sgmii_loopback = drv_data->needs_sgmii_loopback;

- ethqos->pm.link_clk = devm_clk_get(dev, clk_name);
- if (IS_ERR(ethqos->pm.link_clk))
- return dev_err_probe(dev, PTR_ERR(ethqos->pm.link_clk),
- "Failed to get link_clk\n");
+ if (pm_data && pm_data->use_domains) {
+ switch (ethqos->phy_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ ethqos->configure_func = ethqos_configure_rgmii;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ case PHY_INTERFACE_MODE_SGMII:
+ ethqos->configure_func = ethqos_configure_sgmii_pd;
+ plat_dat->mac_finish = ethqos_mac_finish_serdes_pd;
+ break;
+ default:
+ dev_err(dev, "Unsupported phy mode %s\n",
+ phy_modes(ethqos->phy_mode));
+ return -EINVAL;
+ }

- ret = ethqos_clks_config(ethqos, true);
- if (ret)
- return ret;
+ ret = devm_pm_domain_attach_list(dev, &pm_data->pd,
+ &ethqos->pd.pd_list);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to attach power domains\n");
+
+ plat_dat->clks_config = ethqos_pd_clks_config;
+ plat_dat->serdes_powerup = qcom_ethqos_pd_serdes_powerup;
+ plat_dat->serdes_powerdown = qcom_ethqos_pd_serdes_powerdown;
+ plat_dat->exit = qcom_ethqos_pd_exit;
+ plat_dat->init = qcom_ethqos_pd_init;
+ plat_dat->clk_ptp_rate = pm_data->clk_ptp_rate;
+
+ ret = qcom_ethqos_domain_on(ethqos, ETHQOS_PD_SERDES);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to enable the serdes power domain\n");
+
+ ret = devm_add_action_or_reset(dev, ethqos_disable_serdes, ethqos);
+ if (ret)
+ return ret;
+ } else {
+ switch (ethqos->phy_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ ethqos->configure_func = ethqos_configure_rgmii;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ case PHY_INTERFACE_MODE_SGMII:
+ ethqos->configure_func = ethqos_configure_sgmii;
+ plat_dat->mac_finish = ethqos_mac_finish_serdes;
+ break;
+ default:
+ dev_err(dev, "Unsupported phy mode %s\n",
+ phy_modes(ethqos->phy_mode));
+ return -EINVAL;
+ }

- ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos);
- if (ret)
- return ret;
+ ethqos->pm.link_clk = devm_clk_get(dev, clk_name);
+ if (IS_ERR(ethqos->pm.link_clk))
+ return dev_err_probe(dev, PTR_ERR(ethqos->pm.link_clk),
+ "Failed to get link_clk\n");
+
+ ret = ethqos_clks_config(ethqos, true);
+ if (ret)
+ return ret;
+
+ ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos);
+ if (ret)
+ return ret;
+
+ ethqos->pm.serdes_phy = devm_phy_optional_get(dev, "serdes");
+ if (IS_ERR(ethqos->pm.serdes_phy))
+ return dev_err_probe(dev, PTR_ERR(ethqos->pm.serdes_phy),
+ "Failed to get serdes phy\n");

- ethqos->pm.serdes_phy = devm_phy_optional_get(dev, "serdes");
- if (IS_ERR(ethqos->pm.serdes_phy))
- return dev_err_probe(dev, PTR_ERR(ethqos->pm.serdes_phy),
- "Failed to get serdes phy\n");
+ ethqos_set_clk_tx_rate(ethqos, NULL, plat_dat->phy_interface,
+ SPEED_1000);

- ethqos_set_clk_tx_rate(ethqos, NULL, plat_dat->phy_interface,
- SPEED_1000);
+ plat_dat->clks_config = ethqos_clks_config;
+ plat_dat->set_clk_tx_rate = ethqos_set_clk_tx_rate;
+ plat_dat->ptp_clk_freq_config = ethqos_ptp_clk_freq_config;
+
+ if (ethqos->pm.serdes_phy) {
+ plat_dat->serdes_powerup = qcom_ethqos_serdes_powerup;
+ plat_dat->serdes_powerdown = qcom_ethqos_serdes_powerdown;
+ }
+ }

qcom_ethqos_set_sgmii_loopback(ethqos, true);
ethqos_set_func_clk_en(ethqos);

plat_dat->bsp_priv = ethqos;
- plat_dat->set_clk_tx_rate = ethqos_set_clk_tx_rate;
plat_dat->fix_mac_speed = ethqos_fix_mac_speed;
plat_dat->dump_debug_regs = rgmii_dump;
- plat_dat->ptp_clk_freq_config = ethqos_ptp_clk_freq_config;
plat_dat->core_type = DWMAC_CORE_GMAC4;
if (ethqos->has_emac_ge_3)
plat_dat->dwmac4_addrs = &drv_data->dwmac4_addrs;
@@ -877,6 +1099,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev)

static const struct of_device_id qcom_ethqos_match[] = {
{ .compatible = "qcom,qcs404-ethqos", .data = &emac_qcs404_data},
+ { .compatible = "qcom,sa8255p-ethqos", .data = &emac_sa8255p_data},
{ .compatible = "qcom,sa8775p-ethqos", .data = &emac_sa8775p_data},
{ .compatible = "qcom,sc8280xp-ethqos", .data = &emac_sc8280xp_data},
{ .compatible = "qcom,sm8150-ethqos", .data = &emac_sm8150_data},

--
2.47.3