From: Andre Przywara <andre.przywara@arm.com>
To: Icenowy Zheng <uwu@icenowy.me>, Jagan Teki <jagan@amarulasolutions.com>
Cc: u-boot@lists.denx.de, linux-sunxi@lists.linux.dev
Subject: Re: [PATCH 1/2] sunxi: fix SUNIV build when enabling D-Cache
Date: Mon, 17 Oct 2022 10:26:12 +0100 [thread overview]
Message-ID: <ba42f4fd-359a-d748-939b-9eef240fcbce@arm.com> (raw)
In-Reply-To: <20221013132645.2469041-2-uwu@icenowy.me>
On 13/10/2022 14:26, Icenowy Zheng wrote:
> The enable_caches function in architecture-specific board code is only
> necessary for V7A CPUs, code for both V8A and ARM926 have already
> declared this function.
>
> Only provide our implementation of enable_caches() for V7A CPUs.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Merging into sunxi/master.
Cheers,
Andre
> ---
> arch/arm/mach-sunxi/board.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> index 62bb40b8c8..60ccf909db 100644
> --- a/arch/arm/mach-sunxi/board.c
> +++ b/arch/arm/mach-sunxi/board.c
> @@ -488,7 +488,7 @@ void reset_cpu(void)
> }
> #endif
>
> -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
> +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && defined(CONFIG_CPU_V7A)
> void enable_caches(void)
> {
> /* Enable D-cache. I-cache is already enabled in start.S */
next prev parent reply other threads:[~2022-10-17 9:26 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-13 13:26 [PATCH 0/2] sunxi: fix SUNIV D$ support Icenowy Zheng
2022-10-13 13:26 ` [PATCH 1/2] sunxi: fix SUNIV build when enabling D-Cache Icenowy Zheng
2022-10-17 9:26 ` Andre Przywara [this message]
2022-10-13 13:26 ` [PATCH 2/2] configs: sunxi: licheepi_nano: enable D-Cache Icenowy Zheng
2022-10-17 9:27 ` Andre Przywara
2022-10-17 6:47 ` [PATCH 0/2] sunxi: fix SUNIV D$ support Andre Przywara
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