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[9.244.8.156]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4ae23095c5csm876306fac.16.2026.11.09.20.45.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 20:45:17 -0800 (PST) From: Enzo Adriano To: andre.przywara@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, wens@kernel.org, jernej.skrabec@gmail.com, samuel@sholland.org Cc: Maxime Ripard , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Junhui Liu , Jerome Brunet , Pablo Mazzini , Vinicius Pedrosa , Alexander Sverdlin , Jun Yan , Lukas Schmid Subject: [PATCH v3 0/3] arm64: dts: allwinner: add A733/Cubie A7S support Date: Mon, 9 Nov 2026 23:45:15 -0500 Message-ID: X-Mailer: git-send-email 2.53.0 X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series adds the initial Allwinner A733 and Radxa Cubie A7S device trees, enabling UART0, the AXP318W PMIC and the 3.3 V microSD path. Base: v7.4-rc1 (6628e7d4c6b25c8d18f1345e3a20d21829aae7e4). Previous posting (v2): https://lore.kernel.org/r/20261031020640-263f7b05-a7s-dt-v2-0@gmail.com Changes in v3: - Defer SMHC3/mmc3 until it has a tested user; omit binding, node and pins. - Rebase on v7.4-rc1 and list public schema prerequisites. Dependencies, in application order: [1] A733 CCU v6: https://lore.kernel.org/r/20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech [2] AXP318W PMIC v8: https://lore.kernel.org/r/20260910-axp318-regulator-v8-0-e906a61a7f3d@baylibre.com [3] Pinctrl IRQ-bank v3: https://lore.kernel.org/r/20261025142412.112216-1-pmazzini@gmail.com [4] A733 8250_dw v2, patches 2-4: https://lore.kernel.org/r/cover.1792439398.git.vinicius.eduardo.pedrosa@gmail.com [5] Firmware clocks (separate from CCU v6): https://lore.kernel.org/r/20261031020640-263f7b05-a7s-clock@gmail.com [6] Pinctrl voltage-mode fix v3: https://lore.kernel.org/r/20261109-a733-pinctrl-v3@gmail.com DTB/schema checks need only [1] 1/8, [2] 3/5, [3] 2/3 and [4] 3/4, applied in that order before this series. Runtime needs the full CCU, PMIC and IRQ-bank series, [4] patches 2-4, and [5]-[6]. The clock helpers listed in v2 are already in v7.4-rc1. Validation: arm/sunxi.yaml schema check, W=2 CHECK_DTBS=y DTB build and clean git-am reader test passed. The November 4 DT v2 RAM boot exercised UART0, PMIC and MMC0 reads on Cubie A7S with vendor firmware and pinctrl v2; v3 removes a disabled controller and unused pin group. Untested: boot with pinctrl v3, card writes, hotplug, 1.8 V switching, other UART/I2C and storage instances, RTC alarms, EL2/ITS/MSI, and physical BLDO2 voltage. Enzo Adriano (3): dt-bindings: arm: sunxi: document Radxa Cubie A7S arm64: dts: allwinner: add A733 SoC description arm64: dts: allwinner: add Radxa Cubie A7S board .../devicetree/bindings/arm/sunxi.yaml | 5 + arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun60i-a733-cubie-a7s.dts | 284 +++++++++ .../arm64/boot/dts/allwinner/sun60i-a733.dtsi | 601 ++++++++++++++++++ 4 files changed, 891 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun60i-a733-cubie-a7s.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4