From: Samuel Holland <samuel@sholland.org>
To: linux-sunxi@lists.linux.dev
Cc: Kirill <kirill.zhumarin@gmail.com>
Subject: Re: ddr devfreq on H3 - possible?
Date: Thu, 29 Dec 2022 11:29:42 -0600 [thread overview]
Message-ID: <d49cb79d-1405-c2cc-0c33-a768c5bbde91@sholland.org> (raw)
In-Reply-To: <CAKAF0m9DqPjB6C39ZbrRHFrJOodm7WQGTL0x1jduQjNU=JpQ2g@mail.gmail.com>
Hi Kirill,
On 12/28/22 07:10, Kirill wrote:
> I'm trying to use your driver with h3, but have this result:
> ```
> [ 387.306429] sun8i-h3-mbus 1c62000.dram-controller: Detected 32-bit
> DDRx with ODT
> [ 388.450262] sun8i-h3-mbus 1c62000.dram-controller: Using 15554/243750
> (6%) at 1248 MHz
> [ 389.906319] sun8i-h3-mbus 1c62000.dram-controller: Using 1079/243750
> (0%) at 1248 MHz
> [ 389.914314] sun8i-h3-mbus 1c62000.dram-controller: Setting DRAM to
> 156 MHz, tREFI=19, tRFC=28, ODT=disabled
> ```
>
> After this CPU hangs and not responding.
> Is possible (at least theoretically) to use this driver with H3?
Yes, although it will need some help from firmware. If you look at the
vendor driver[1] (pick any random Allwinner 4.9 tree), you will see
there is no mdfs_dfs() implementation for CONFIG_ARCH_SUN8IW7P1 (H3).
The driver always calls mdfs_main(), which is a standalone program
loaded to SRAM. The reason seems to be that the MDFS hardware is broken,
as you found out.
Something like this standalone MDFS application is not upstreamable, but
conveniently we already have some firmware running from SRAM, namely
U-Boot's PSCI/secure monitor implementation. And Allwinner already has
some chips where they call a SMC to do this MDFS procedure[2]. So we can
reuse that SMC function ID, and put the code in in the secure monitor.
I've thrown together U-Boot[3] and Linux[4] patches as a proof of concept.
It works, though it did lock up once after playing with the devfreq
sysfs for several minutes. The contents of sunxi_dram_dvfs_req() are
just copied from the vendor driver; they could surely be improved.
The U-Boot patch is based on my series adding Crust support for H3, so I
could have interactive peek/poke from the AR100 even when the DRAM
controller is dead. It shouldn't be too hard to rebase that out and move
the code to psci.c.
I'm not sure the best way to upstream the changes to psci.S. Probably we
need some platform callback to handle unknown function IDs.
Regards,
Samuel
[1]:
https://github.com/Tina-Linux/tina-v83x-linux-4.9/blob/master/drivers/devfreq/dramfreq/sunxi-ddrfreq.c#L1411
[2]:
https://github.com/Tina-Linux/tina-v83x-linux-4.9/blob/master/drivers/devfreq/sunxi-mdfs.h#L38
[3]: https://github.com/smaeul/u-boot/commits/patch/h3-dram-devfreq
[4]: https://github.com/smaeul/linux/commits/wip/devfreq-a83t
next parent reply other threads:[~2022-12-29 17:29 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CAKAF0m9DqPjB6C39ZbrRHFrJOodm7WQGTL0x1jduQjNU=JpQ2g@mail.gmail.com>
2022-12-29 17:29 ` Samuel Holland [this message]
2022-12-31 11:15 ` ddr devfreq on H3 - possible? Kirill
2022-12-31 20:45 ` Samuel Holland
2023-01-01 21:40 ` Kirill
2023-01-01 22:20 ` Samuel Holland
2023-01-02 2:20 ` Kirill
2023-01-04 23:26 ` Kirill
2023-01-05 2:47 ` Kirill
2023-01-05 20:57 ` Kirill
2023-01-06 1:18 ` Kirill
2023-01-07 16:40 ` Kirill
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