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([2a0d:3344:2712:7e10:4d59:d956:544f:d65c]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e619b8343sm25823335e9.2.2025.10.01.00.25.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 01 Oct 2025 00:25:08 -0700 (PDT) Message-ID: Date: Wed, 1 Oct 2025 09:25:07 +0200 Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next v8 2/2] net: stmmac: Add support for Allwinner A523 GMAC200 To: Jakub Kicinski , Heiner Kallweit , Russell King , Chen-Yu Tsai Cc: Andrew Lunn , "David S. Miller" , Eric Dumazet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec References: <20250925191600.3306595-1-wens@kernel.org> <20250925191600.3306595-3-wens@kernel.org> <20250929180804.3bd18dd9@kernel.org> <20250930172022.3a6dd03e@kernel.org> From: Paolo Abeni In-Reply-To: <20250930172022.3a6dd03e@kernel.org> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: OXuBkafA9g8da3_DJF9rOqPnSK3RmCWY6rKni-4xEdw_1759303510 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 10/1/25 2:20 AM, Jakub Kicinski wrote: > On Mon, 29 Sep 2025 18:08:04 -0700 Jakub Kicinski wrote: >> On Fri, 26 Sep 2025 03:15:59 +0800 Chen-Yu Tsai wrote: >>> The Allwinner A523 SoC family has a second Ethernet controller, called >>> the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for >>> numbering. This controller, according to BSP sources, is fully >>> compatible with a slightly newer version of the Synopsys DWMAC core. >>> The glue layer around the controller is the same as found around older >>> DWMAC cores on Allwinner SoCs. The only slight difference is that since >>> this is the second controller on the SoC, the register for the clock >>> delay controls is at a different offset. Last, the integration includes >>> a dedicated clock gate for the memory bus and the whole thing is put in >>> a separately controllable power domain. >> >> Hi Andrew, does this look good ? >> >> thread: https://lore.kernel.org/20250925191600.3306595-3-wens@kernel.org > > Adding Heiner and Russell, in case Andrew is AFK. > > We need an ack from PHY maintainers, the patch seems to be setting > delays regardless of the exact RMII mode. I don't know these things.. The net-next PR is upon us, let's defer even this series to the next cycle. @Chen-Yu Tsai: please re-post it when net-next will reopen after Oct 12th, thanks! Paolo