Re: [PATCH] phy: allwinner: sun4i-usb: disable the PHY2 PMU clock after SIDDQ setup

[Andre Przywara <andre.przywara@arm.com>]

Hi,

On 7/6/26 11:35, raoxu wrote:
> From: Xu Rao <raoxu@uniontech.com>
> 
> sun4i_usb_phy_init() temporarily enables PHY2's clk2 when a SoC needs
> PHY2 SIDDQ setup while initializing another PHY. However, after updating
> PHY2's PMU register it disables the clk2 pointer from the PHY currently
> being initialized.
> 
> This leaves PHY2's clk2 enabled and also drops an extra reference from
> the current PHY's clk2, causing the prepare/enable accounting to become
> unbalanced.
> 
> Disable the same PHY2 clk2 that was enabled for the auxiliary PMU access.
> 
> Signed-off-by: Xu Rao <raoxu@uniontech.com>
> ---
>   drivers/phy/allwinner/phy-sun4i-usb.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
> index e2fbf8ccf99e..839856c09e30 100644
> --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> @@ -318,7 +318,7 @@ static int sun4i_usb_phy_init(struct phy *_phy)
>   			writel(val, phy2->pmu + REG_HCI_PHY_CTL);
>   		}
> 
> -		clk_disable_unprepare(phy->clk2);
> +		clk_disable_unprepare(phy2->clk2);

Interesting, this looks about right, and matches the comment above, 
noting that phy2->clk2 is just temporarily needed. I don't remember 
further details, only that this workaround was quite annoying and messy ;-)

However I am wondering how this worked so far: This should sabotage the 
access to the local REG_HCI_PHY_CTL access in the next few lines ...
Any idea why this worked nevertheless?

Thanks,
Andre

>   	}
> 
>   	if (phy->pmu && data->cfg->hci_phy_ctl_clear) {
> --
> 2.50.1
>