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[46.150.62.216]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4549130549bsm12104013f8f.18.2026.05.09.06.00.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 May 2026 06:00:30 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: =?UTF-8?B?T25kxZllaiBKaXJtYW4gPG1lZ2lAeGZmLmN6PiwgSmVybmVqIMWga3JhYmVj?= , linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Lee Jones , Chen-Yu Tsai Subject: Re: [PATCH] mfd: axp20x: Change volatile ranges on axp803 Date: Sat, 09 May 2026 15:00:29 +0200 Message-ID: In-Reply-To: References: <20260315124932.3669260-1-megi@xff.cz> <5084920.31r3eYUQgx@jernej-laptop> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne sobota, 21. marec 2026 ob 19:26:43 Srednjeevropski poletni =C4=8Das je = Ond=C5=99ej Jirman napisal(a): > On Sat, Mar 21, 2026 at 07:25:49AM +0100, Jernej =C5=A0krabec wrote: > > Dne nedelja, 15. marec 2026 ob 13:49:31 Srednjeevropski standardni =C4= =8Das je Ond=C5=99ej Jirman napisal(a): > > > From: Ondrej Jirman > > >=20 > > > Regulator control registers can be cached. They don't update by > > > themselves. Enable cache on them, to speed up voltage changes, > > > particularly DCDC2 which needs to be handled quickly due to being used > > > for CPUX cores and is changed very frequently by some cpufreq schedul= ers. > >=20 > > That's not really the case, DCDC2-DCDC6 registers have DVM finished sta= tus > > bit, which is volatile and it is right to have them in volatile range. > > However, it is true that other registers are non-volatile, so that rang= e can > > be considerably shrinked. It seems that AXP288 have same register layout > > but I can't say for sure (I only found datasheet for AXP288C), so it's = best > > to leave it alone and apply changes only to AXP803.=20 >=20 > While true, it's not used by any kernel drivers, and having the whole reg= ister > marked volatile for a single unused bit is contributing 10s of % of perma= nent > CPU load just from cpufreq DVFS operations alone when using schedutil gov= ernor, > which is doing DVFS hundred or more times per second. >=20 > If someone will want to use this bit in the regulator driver, they can us= e eg. > regmap_read_bypassed() to access the bit, while keepig the other parts of > regulator implementation performant. This sounds like a good compromise. >=20 > But I guess it may deserve a comment in the code. =46or sure. BR Jernej >=20 > Kind regards, > o. >=20 > > Best regards, > > Jernej > >=20 > > >=20 > > > This shrinks register access over RSB bus to one write per voltage > > > change (down from 4 or so). > > >=20 > > > Signed-off-by: Ondrej Jirman > > > --- > > > drivers/mfd/axp20x.c | 28 +++++++++++++++++++++++++++- > > > 1 file changed, 27 insertions(+), 1 deletion(-) > > >=20 > > > diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c > > > index 0d0d40972eb8..2ea409029d2f 100644 > > > --- a/drivers/mfd/axp20x.c > > > +++ b/drivers/mfd/axp20x.c > > > @@ -172,6 +172,18 @@ static const struct regmap_range axp288_volatile= _ranges[] =3D { > > > regmap_reg_range(AXP20X_FG_RES, AXP288_FG_CC_CAP_REG), > > > }; > > > =20 > > > +static const struct regmap_range axp803_volatile_ranges[] =3D { > > > + regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP288_POWER_REASON), > > > + regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL), > > > + regmap_reg_range(AXP288_BC_DET_STAT, AXP20X_VBUS_IPSOUT_MGMT), > > > + regmap_reg_range(AXP20X_CHRG_BAK_CTRL, AXP20X_CHRG_BAK_CTRL), > > > + regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L), > > > + regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL), > > > + regmap_reg_range(AXP20X_GPIO1_CTRL, AXP22X_GPIO_STATE), > > > + regmap_reg_range(AXP288_RT_BATT_V_H, AXP288_RT_BATT_V_L), > > > + regmap_reg_range(AXP20X_FG_RES, AXP288_FG_CC_CAP_REG), > > > +}; > > > + > > > static const struct regmap_access_table axp288_writeable_table =3D { > > > .yes_ranges =3D axp288_writeable_ranges, > > > .n_yes_ranges =3D ARRAY_SIZE(axp288_writeable_ranges), > > > @@ -182,6 +194,11 @@ static const struct regmap_access_table axp288_v= olatile_table =3D { > > > .n_yes_ranges =3D ARRAY_SIZE(axp288_volatile_ranges), > > > }; > > > =20 > > > +static const struct regmap_access_table axp803_volatile_table =3D { > > > + .yes_ranges =3D axp803_volatile_ranges, > > > + .n_yes_ranges =3D ARRAY_SIZE(axp803_volatile_ranges), > > > +}; > > > + > > > static const struct regmap_range axp806_writeable_ranges[] =3D { > > > regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_DATACACHE(3)), > > > regmap_reg_range(AXP806_PWR_OUT_CTRL1, AXP806_CLDO3_V_CTRL), > > > @@ -456,6 +473,15 @@ static const struct regmap_config axp22x_regmap_= config =3D { > > > .cache_type =3D REGCACHE_MAPLE, > > > }; > > > =20 > > > +static const struct regmap_config axp803_regmap_config =3D { > > > + .reg_bits =3D 8, > > > + .val_bits =3D 8, > > > + .wr_table =3D &axp288_writeable_table, > > > + .volatile_table =3D &axp803_volatile_table, > > > + .max_register =3D AXP288_FG_TUNE5, > > > + .cache_type =3D REGCACHE_MAPLE, > > > +}; > > > + > > > static const struct regmap_config axp288_regmap_config =3D { > > > .reg_bits =3D 8, > > > .val_bits =3D 8, > > > @@ -1368,7 +1394,7 @@ int axp20x_match_device(struct axp20x_dev *axp2= 0x) > > > case AXP803_ID: > > > axp20x->nr_cells =3D ARRAY_SIZE(axp803_cells); > > > axp20x->cells =3D axp803_cells; > > > - axp20x->regmap_cfg =3D &axp288_regmap_config; > > > + axp20x->regmap_cfg =3D &axp803_regmap_config; > > > axp20x->regmap_irq_chip =3D &axp803_regmap_irq_chip; > > > break; > > > case AXP806_ID: > > >=20 > >=20 > >=20 > >=20 > >=20 >=20