Re: [PATCH 2/3] ARM: sunxi: select HAVE_SHARED_GPIOS

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] ARM: sunxi: HAVE_SHARED_GPIOS ignores 3-cell sunxi SoC GPIO bindings
--

commit 08b8c5df755142dacaed1d91af688663b9db7e82
Author: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>

ARM: sunxi: select HAVE_SHARED_GPIOS

This commit selects HAVE_SHARED_GPIOS for ARCH_SUNXI to enable automated
management of shared GPIOs via the GPIO shared proxy module on sunxi
platforms.

> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index e015f2497111a..b62e8518e2704 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -5,6 +5,7 @@ menuconfig ARCH_SUNXI
>  	select ARCH_HAS_RESET_CONTROLLER
>  	select CLKSRC_MMIO
>  	select GPIOLIB
> +	select HAVE_SHARED_GPIOS

[Severity: Medium]
Does selecting HAVE_SHARED_GPIOS here actually work for Allwinner sunxi SoC
GPIO controllers?

Allwinner sunxi pinctrl/GPIO controllers (&pio and &r_pio) use 3-cell GPIO
specifiers (#gpio-cells = <3>: bank, pin, flags), as translated in
drivers/pinctrl/sunxi/pinctrl-sunxi.c:sunxi_pinctrl_gpio_of_xlate():

static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
				const struct of_phandle_args *gpiospec,
				u32 *flags)
{
	int pin, base;

	base = PINS_PER_BANK * gpiospec->args[0];
	pin = base + gpiospec->args[1];

For example, in arch/arm/boot/dts/allwinner/sunxi-libretech-all-h3-cc.dtsi,
reg_vcc1v2 and reg_vdd_cpux share a GPIO using a 3-cell specifier:

	gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */

However, during boot, gpio_shared_of_scan() -> gpio_shared_of_traverse() in
drivers/gpio/gpiolib-shared.c skips any GPIO specifier that does not have
exactly 2 cells:

	if (args.args_count != 2)
		continue;

Additionally, struct gpio_shared_entry only records a single cell in
entry->offset, and gpiochip_setup_shared() in drivers/gpio/gpiolib-shared.c
hardcodes a 2-cell specifier with only args[0] populated when invoking
gc->of_xlate():

	gpiospec.np = to_of_node(entry->fwnode);
	gpiospec.args_count = 2;
	gpiospec.args[0] = entry->offset;

	ret = gc->of_xlate(gc, &gpiospec, NULL);

Wouldn't this cause gpiolib-shared to ignore all shared sunxi SoC GPIOs in
device tree, so any consumer relying on HAVE_SHARED_GPIOS rather than
GPIOD_FLAGS_BIT_NONEXCLUSIVE fails with -EBUSY?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261103-panel-mipi-non-exclusive-gpios-v1-0-aa862c1d71e3@oss.qualcomm.com?part=2