Re: [PATCH v7 08/13] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP

[Manikanta Maddireddy <mmaddireddy@nvidia.com>]

On 05/03/26 3:49 pm, Manivannan Sadhasivam wrote:
> On Tue, Mar 03, 2026 at 12:24:43PM +0530, Manikanta Maddireddy wrote:
>> From: Vidya Sagar <vidyas@nvidia.com>
>>
>> PERST# and CLKREQ# pinctrl settings should be applied for both Root Port
>> and Endpoint mode. Move pinctrl_pm_select_default_state() function call
>> from Root Port specific configuration function to probe().
>>
> 
> Why should this driver care about setting default pinctrl state? Why can't it
> rely on the pinctrl framework as like other drivers?
> 
> - Mani

pinctrl framework doesn't know if PCIe controller is going to be 
configured in Endpoint or Root port mode. In Root port mode PERST# 
signal should be configured as special function IO pin(SFIO) and in 
Endpoint mode it should be configured as general purpose IO pin(GPIO). 
So, PCIe driver should request appropriate pinctl values.

- Manikanta

> 
>> Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
>> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
>> Tested-by: Jon Hunter <jonathanh@nvidia.com>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>> Changes V5 -> V7: None
>> Changes V4 -> V5: Use dev_err_probe() function
>> Changes V1 -> V4: None
>>
>>   drivers/pci/controller/dwc/pcie-tegra194.c | 10 ++++------
>>   1 file changed, 4 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index b50229df890e..5b79d3c28ba6 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -1598,12 +1598,6 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
>>   		goto fail_pm_get_sync;
>>   	}
>>   
>> -	ret = pinctrl_pm_select_default_state(dev);
>> -	if (ret < 0) {
>> -		dev_err(dev, "Failed to configure sideband pins: %d\n", ret);
>> -		goto fail_pm_get_sync;
>> -	}
>> -
>>   	ret = tegra_pcie_init_controller(pcie);
>>   	if (ret < 0) {
>>   		dev_err(dev, "Failed to initialize controller: %d\n", ret);
>> @@ -2077,6 +2071,10 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
>>   	pp = &pci->pp;
>>   	pp->num_vectors = MAX_MSI_IRQS;
>>   
>> +	ret = pinctrl_pm_select_default_state(dev);
>> +	if (ret < 0)
>> +		return dev_err_probe(dev, ret, "Failed to configure sideband pins: %d\n", ret);
>> +
>>   	ret = tegra_pcie_dw_parse_dt(pcie);
>>   	if (ret < 0) {
>>   		const char *level = KERN_ERR;
>> -- 
>> 2.34.1
>>
> 

-- 
nvpublic