From: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org,
josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: [PATCH] ARM: tegra: Re-add removed SoC id macro to tegra_resume()
Date: Wed, 8 Oct 2014 22:54:10 +0400 [thread overview]
Message-ID: <1412794450-9060-1-git-send-email-digetx@gmail.com> (raw)
Commit d127e9c5c5bc1ee22a7b1fe804397cddd132f756 ("ARM: tegra: make tegra_resume
can work with current and later chips") removed tegra_get_soc_id macro leaving
used cpu register unassigned and as result causing execution of unintended code
on tegra20. Fix it by re-adding macro.
Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm/mach-tegra/reset-handler.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 7b2baab..71be4af 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -51,6 +51,7 @@ ENTRY(tegra_resume)
THUMB( it ne )
bne cpu_resume @ no
+ tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
/* Are we on Tegra20? */
cmp r6, #TEGRA20
beq 1f @ Yes
--
2.1.1
next reply other threads:[~2014-10-08 18:54 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-08 18:54 Dmitry Osipenko [this message]
[not found] ` <1412794450-9060-1-git-send-email-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-10-08 19:01 ` [PATCH] ARM: tegra: Re-add removed SoC id macro to tegra_resume() Felipe Balbi
2014-10-08 19:04 ` Felipe Balbi
2014-10-08 19:24 ` [PATCH V2] " Dmitry Osipenko
[not found] ` <1412796255-10589-1-git-send-email-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-10-09 22:10 ` Dmitry Osipenko
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