From: David Ung <davidu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: David Ung <davidu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Subject: [PATCH] gpu: drm: tegra: Adjust dsi phy timing
Date: Mon, 1 Dec 2014 16:52:02 -0800 [thread overview]
Message-ID: <1417481522-32110-1-git-send-email-davidu@nvidia.com> (raw)
Fixing DSI phy setting of HS trail timings.
Signed-off-by: David Ung <davidu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
drivers/gpu/drm/tegra/mipi-phy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/tegra/mipi-phy.c b/drivers/gpu/drm/tegra/mipi-phy.c
index 486d19d..974bc68 100644
--- a/drivers/gpu/drm/tegra/mipi-phy.c
+++ b/drivers/gpu/drm/tegra/mipi-phy.c
@@ -34,7 +34,7 @@ int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
timing->hszero = 145 + 5 * period;
timing->hssettle = 85 + 6 * period;
timing->hsskip = 40;
- timing->hstrail = max(8 * period, 60 + 4 * period);
+ timing->hstrail = 3 * period * 8 + max(8 * period, 60 + 4 * period);
timing->init = 100000;
timing->lpx = 60;
timing->taget = 5 * timing->lpx;
--
1.8.1.5
next reply other threads:[~2014-12-02 0:52 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-02 0:52 David Ung [this message]
[not found] ` <1417481522-32110-1-git-send-email-davidu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-12-02 9:37 ` [PATCH] gpu: drm: tegra: Adjust dsi phy timing Thierry Reding
2014-12-03 1:32 ` David Ung
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