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From: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Peter De Schrijver
	<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Mike Turquette
	<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
	Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
	Thierry Reding
	<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	Alexandre Courbot
	<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Subject: [PATCH v2 01/19] clk: tegra: Modify tegra_audio_clk_init to accept more plls
Date: Wed, 29 Apr 2015 13:21:31 -0400	[thread overview]
Message-ID: <1430328109-537-2-git-send-email-rklein@nvidia.com> (raw)
In-Reply-To: <1430328109-537-1-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

tegra_audio_clk_init was written expecting a single PLL to be
passed in directly. Change this to accept an array which will
allow for supporting multiple plls and specifying specific data
about them, like their parent, which may change over time.

Signed-off-by: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 drivers/clk/tegra/clk-tegra-audio.c |   25 ++++++++++++++++++-------
 drivers/clk/tegra/clk-tegra114.c    |    7 ++++++-
 drivers/clk/tegra/clk-tegra124.c    |    7 ++++++-
 drivers/clk/tegra/clk-tegra30.c     |    7 ++++++-
 drivers/clk/tegra/clk.h             |   18 +++++++++++++++++-
 5 files changed, 53 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra-audio.c b/drivers/clk/tegra/clk-tegra-audio.c
index 5c38aab2c5b8..b7b88660f261 100644
--- a/drivers/clk/tegra/clk-tegra-audio.c
+++ b/drivers/clk/tegra/clk-tegra-audio.c
@@ -126,18 +126,29 @@ static struct tegra_audio2x_clk_initdata audio2x_clks[] = {
 
 void __init tegra_audio_clk_init(void __iomem *clk_base,
 			void __iomem *pmc_base, struct tegra_clk *tegra_clks,
-			struct tegra_clk_pll_params *pll_a_params)
+			struct tegra_audio_clk_info *audio_info,
+			int num_plls)
 {
 	struct clk *clk;
 	struct clk **dt_clk;
 	int i;
 
-	/* PLLA */
-	dt_clk = tegra_lookup_dt_id(tegra_clk_pll_a, tegra_clks);
-	if (dt_clk) {
-		clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base,
-				pmc_base, 0, pll_a_params, NULL);
-		*dt_clk = clk;
+	if (!audio_info || num_plls < 1) {
+		pr_err("No audio data passed to tegra_audio_clk_init\n");
+		WARN_ON(1);
+		return;
+	}
+
+	for (i = 0; i < num_plls; i++) {
+		struct tegra_audio_clk_info *info = &audio_info[i];
+
+		dt_clk = tegra_lookup_dt_id(info->clk_id, tegra_clks);
+		if (dt_clk) {
+			clk = tegra_clk_register_pll(info->name, info->parent,
+					clk_base, pmc_base, 0, info->pll_params,
+					NULL);
+			*dt_clk = clk;
+		}
 	}
 
 	/* PLLA_OUT0 */
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 8237d16b4075..0d67efb3dd6a 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -935,6 +935,10 @@ static u32 mux_pllm_pllc2_c_c3_pllp_plla_idx[] = {
 	[0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
 };
 
+static struct tegra_audio_clk_info tegra114_audio_plls[] = {
+	{ "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
+};
+
 static struct clk **clks;
 
 static unsigned long osc_freq;
@@ -1483,7 +1487,8 @@ static void __init tegra114_clock_init(struct device_node *np)
 	tegra114_fixed_clk_init(clk_base);
 	tegra114_pll_init(clk_base, pmc_base);
 	tegra114_periph_clk_init(clk_base, pmc_base);
-	tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, &pll_a_params);
+	tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
+			     &tegra114_audio_plls, 1);
 	tegra_pmc_clk_init(pmc_base, tegra114_clks);
 	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
 					&pll_x_params);
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 9d626c8d558a..4900429255bc 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1400,6 +1400,10 @@ static struct tegra_clk_init_table tegra132_init_table[] __initdata = {
 	{TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
 };
 
+static struct tegra_audio_clk_info tegra124_audio_plls[] = {
+	{ "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
+};
+
 /**
  * tegra124_clock_apply_init_table - initialize clocks on Tegra124 SoCs
  *
@@ -1476,7 +1480,8 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
 	tegra_fixed_clk_init(tegra124_clks);
 	tegra124_pll_init(clk_base, pmc_base);
 	tegra124_periph_clk_init(clk_base, pmc_base);
-	tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params);
+	tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,
+			     tegra124_audio_plls, 1);
 	tegra_pmc_clk_init(pmc_base, tegra124_clks);
 
 	/* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 4b26509fc218..3198c7b7946c 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1406,6 +1406,10 @@ static const struct of_device_id pmc_match[] __initconst = {
 	{},
 };
 
+static struct tegra_audio_clk_info tegra30_audio_plls[] = {
+	{ "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
+};
+
 static void __init tegra30_clock_init(struct device_node *np)
 {
 	struct device_node *node;
@@ -1443,7 +1447,8 @@ static void __init tegra30_clock_init(struct device_node *np)
 	tegra30_pll_init();
 	tegra30_super_clk_init();
 	tegra30_periph_clk_init();
-	tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks, &pll_a_params);
+	tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
+			     &tegra30_audio_plls, 1);
 	tegra_pmc_clk_init(pmc_base, tegra30_clks);
 
 	tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 1bb1afa14c81..2abb6e1b7d93 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -258,6 +258,21 @@ struct tegra_clk_pll {
 
 #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
 
+/**
+ * struct tegra_audio_clk_info - Tegra Audio Clk Information
+ *
+ * @name:	name for the audio pll
+ * @pll_params:	pll_params for audio pll
+ * @clk_id:	clk_ids for the audio pll
+ * @parent:	name of the parent of the audio pll
+ */
+struct tegra_audio_clk_info {
+	char *name;
+	struct tegra_clk_pll_params *pll_params;
+	int clk_id;
+	char *parent;
+};
+
 extern const struct clk_ops tegra_clk_pll_ops;
 extern const struct clk_ops tegra_clk_plle_ops;
 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
@@ -607,7 +622,8 @@ void tegra_register_devclks(struct tegra_devclk *dev_clks, int num);
 
 void tegra_audio_clk_init(void __iomem *clk_base,
 			void __iomem *pmc_base, struct tegra_clk *tegra_clks,
-			struct tegra_clk_pll_params *pll_params);
+			struct tegra_audio_clk_info *audio_info,
+			int num_plls);
 
 void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
 			struct tegra_clk *tegra_clks,
-- 
1.7.9.5

  parent reply	other threads:[~2015-04-29 17:21 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-29 17:21 [PATCH v2 00/19] Tegra210 Clock Support Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 02/19] clk: tegra: periph: add new periph clks and muxes for Tegra210 Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 04/19] clk: tegra: pll: simplify clk_enable_path Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 05/19] clk: tegra: pll: update warning msg Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 06/19] clk: tegra: pll-params: change misc_reg count from 3 -> 6 Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 07/19] clk: tegra: pll: Don't unconditionally set LOCK flags Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 08/19] clk: tegra: pll: Add logic for handling SDM data Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 09/19] clk: tegra: pll: Add logic for SS Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 11/19] clk: tegra: pll: Add code to handle if resets are supported by PLL Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 12/19] clk: tegra: pll: Add specialized logic for T210 Rhyland Klein
     [not found]   ` <1430328109-537-13-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-04-29 18:27     ` Andrew Bresticker
2015-04-29 21:42       ` Rhyland Klein
     [not found] ` <1430328109-537-1-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-04-29 17:21   ` Rhyland Klein [this message]
2015-04-29 17:21   ` [PATCH v2 03/19] clk: tegra: pll: add tegra_pll_wait_for_lock to clk header Rhyland Klein
2015-04-29 17:21   ` [PATCH v2 10/19] clk: tegra: pll: Add logic for out-of-table rates for T210 Rhyland Klein
2015-04-29 17:21   ` [PATCH v2 13/19] clk: tegra: pll: Add support for PLLMB " Rhyland Klein
2015-04-30 10:11     ` Peter De Schrijver
2015-04-29 17:21   ` [PATCH v2 14/19] clk: tegra: pll: Adjust vco_min if SDM present Rhyland Klein
2015-04-29 17:21   ` [PATCH v2 15/19] clk: tegra: pll: Add dyn_ramp callback Rhyland Klein
2015-04-29 17:21   ` [PATCH v2 16/19] clk: tegra: pll: Add Set_default logic Rhyland Klein
     [not found]     ` <1430328109-537-17-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-04-30 10:12       ` Peter De Schrijver
     [not found]         ` <20150430101225.GU3097-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2015-04-30 15:31           ` Rhyland Klein
     [not found]             ` <55424ACA.9010406-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-11 11:50               ` Peter De Schrijver
     [not found]                 ` <20150511115036.GG22637-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2015-05-11 15:07                   ` Rhyland Klein
2015-04-29 17:21   ` [PATCH v2 17/19] clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate Rhyland Klein
2015-04-29 17:21   ` [PATCH v2 18/19] clk: tegra: Add Super Gen5 Logic Rhyland Klein
2015-04-29 17:21   ` [PATCH v2 19/19] clk: tegra210: add support for Tegra210 clocks Rhyland Klein
2015-04-30 20:43     ` Andrew Bresticker
     [not found]       ` <CAL1qeaHdjb57D8U-NBeyicV=JP2pNkyx3Xfn2RDgWivdw5jWNg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-04-30 20:57         ` Rhyland Klein

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