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From: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Peter De Schrijver
	<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Mike Turquette
	<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
	Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
	Thierry Reding
	<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	Alexandre Courbot
	<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Subject: [PATCH v2 03/19] clk: tegra: pll: add tegra_pll_wait_for_lock to clk header
Date: Wed, 29 Apr 2015 13:21:33 -0400	[thread overview]
Message-ID: <1430328109-537-4-git-send-email-rklein@nvidia.com> (raw)
In-Reply-To: <1430328109-537-1-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Create a wrapper interface to make use of the existing
clk_pll_wait_for_lock. This will be useful for implementations
of callbacks in Tegra SoC specific clock drivers.

Signed-off-by: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 drivers/clk/tegra/clk-pll.c |    5 +++++
 drivers/clk/tegra/clk.h     |    1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 05c6d08a6695..b9a739ce4b98 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -269,6 +269,11 @@ static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
 	return -1;
 }
 
+int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
+{
+	return clk_pll_wait_for_lock(pll);
+}
+
 static int clk_pll_is_enabled(struct clk_hw *hw)
 {
 	struct tegra_clk_pll *pll = to_clk_pll(hw);
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 2abb6e1b7d93..4ea8b5b089cd 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -659,5 +659,6 @@ void tegra114_clock_deassert_dfll_dvco_reset(void);
 
 typedef void (*tegra_clk_apply_init_table_func)(void);
 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
+int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
 
 #endif /* TEGRA_CLK_H */
-- 
1.7.9.5

  parent reply	other threads:[~2015-04-29 17:21 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-29 17:21 [PATCH v2 00/19] Tegra210 Clock Support Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 02/19] clk: tegra: periph: add new periph clks and muxes for Tegra210 Rhyland Klein
     [not found] ` <1430328109-537-1-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-04-29 17:21   ` [PATCH v2 01/19] clk: tegra: Modify tegra_audio_clk_init to accept more plls Rhyland Klein
2015-04-29 17:21   ` Rhyland Klein [this message]
2015-04-29 17:21   ` [PATCH v2 10/19] clk: tegra: pll: Add logic for out-of-table rates for T210 Rhyland Klein
2015-04-29 17:21   ` [PATCH v2 13/19] clk: tegra: pll: Add support for PLLMB " Rhyland Klein
2015-04-30 10:11     ` Peter De Schrijver
2015-04-29 17:21   ` [PATCH v2 14/19] clk: tegra: pll: Adjust vco_min if SDM present Rhyland Klein
2015-04-29 17:21   ` [PATCH v2 15/19] clk: tegra: pll: Add dyn_ramp callback Rhyland Klein
2015-04-29 17:21   ` [PATCH v2 16/19] clk: tegra: pll: Add Set_default logic Rhyland Klein
     [not found]     ` <1430328109-537-17-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-04-30 10:12       ` Peter De Schrijver
     [not found]         ` <20150430101225.GU3097-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2015-04-30 15:31           ` Rhyland Klein
     [not found]             ` <55424ACA.9010406-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-11 11:50               ` Peter De Schrijver
     [not found]                 ` <20150511115036.GG22637-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2015-05-11 15:07                   ` Rhyland Klein
2015-04-29 17:21   ` [PATCH v2 17/19] clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate Rhyland Klein
2015-04-29 17:21   ` [PATCH v2 18/19] clk: tegra: Add Super Gen5 Logic Rhyland Klein
2015-04-29 17:21   ` [PATCH v2 19/19] clk: tegra210: add support for Tegra210 clocks Rhyland Klein
2015-04-30 20:43     ` Andrew Bresticker
     [not found]       ` <CAL1qeaHdjb57D8U-NBeyicV=JP2pNkyx3Xfn2RDgWivdw5jWNg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-04-30 20:57         ` Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 04/19] clk: tegra: pll: simplify clk_enable_path Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 05/19] clk: tegra: pll: update warning msg Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 06/19] clk: tegra: pll-params: change misc_reg count from 3 -> 6 Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 07/19] clk: tegra: pll: Don't unconditionally set LOCK flags Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 08/19] clk: tegra: pll: Add logic for handling SDM data Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 09/19] clk: tegra: pll: Add logic for SS Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 11/19] clk: tegra: pll: Add code to handle if resets are supported by PLL Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 12/19] clk: tegra: pll: Add specialized logic for T210 Rhyland Klein
     [not found]   ` <1430328109-537-13-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-04-29 18:27     ` Andrew Bresticker
2015-04-29 21:42       ` Rhyland Klein

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