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From: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Peter De Schrijver
	<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Mike Turquette
	<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
	Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
	Thierry Reding
	<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	Alexandre Courbot
	<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Subject: [PATCH v3 03/20] clk: tegra: pll: add tegra_pll_wait_for_lock to clk header
Date: Fri, 1 May 2015 14:53:50 -0400	[thread overview]
Message-ID: <1430506447-29074-4-git-send-email-rklein@nvidia.com> (raw)
In-Reply-To: <1430506447-29074-1-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Create a wrapper interface to make use of the existing
clk_pll_wait_for_lock. This will be useful for implementations
of callbacks in Tegra SoC specific clock drivers.

Signed-off-by: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 drivers/clk/tegra/clk-pll.c |    5 +++++
 drivers/clk/tegra/clk.h     |    1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 05c6d08a6695..b9a739ce4b98 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -269,6 +269,11 @@ static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
 	return -1;
 }
 
+int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
+{
+	return clk_pll_wait_for_lock(pll);
+}
+
 static int clk_pll_is_enabled(struct clk_hw *hw)
 {
 	struct tegra_clk_pll *pll = to_clk_pll(hw);
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 2abb6e1b7d93..4ea8b5b089cd 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -659,5 +659,6 @@ void tegra114_clock_deassert_dfll_dvco_reset(void);
 
 typedef void (*tegra_clk_apply_init_table_func)(void);
 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
+int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
 
 #endif /* TEGRA_CLK_H */
-- 
1.7.9.5

  parent reply	other threads:[~2015-05-01 18:53 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-01 18:53 [PATCH v3 00/20] Tegra210 Clock Support Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 01/20] clk: tegra: Modify tegra_audio_clk_init to accept more plls Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 04/20] clk: tegra: pll: simplify clk_enable_path Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 05/20] clk: tegra: pll: update warning msg Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 06/20] clk: tegra: pll-params: change misc_reg count from 3 -> 6 Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 07/20] clk: tegra: pll: Don't unconditionally set LOCK flags Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 08/20] clk: tegra: pll: Add logic for handling SDM data Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 09/20] clk: tegra: pll: Add logic for SS Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 10/20] clk: tegra: pll: Add logic for out-of-table rates for T210 Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 11/20] clk: tegra: pll: Add code to handle if resets are supported by PLL Rhyland Klein
2015-05-01 18:53 ` [PATCH v3 12/20] clk: tegra: pll: Add specialized logic for T210 Rhyland Klein
     [not found]   ` <1430506447-29074-13-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-02  3:12     ` Jim Lin
     [not found]       ` <3e078ce64eff4ac992900523b1b67f19-Mplb3Xlf2OrYuxH7O460wFaTQe2KTcn/@public.gmane.org>
2015-05-04 15:40         ` Rhyland Klein
2015-05-01 18:54 ` [PATCH v3 13/20] clk: tegra: pll: Add support for PLLMB " Rhyland Klein
2015-05-01 18:54 ` [PATCH v3 15/20] clk: tegra: pll: Add dyn_ramp callback Rhyland Klein
2015-05-01 18:54 ` [PATCH v3 16/20] clk: tegra: pll: Add Set_default logic Rhyland Klein
     [not found] ` <1430506447-29074-1-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-01 18:53   ` [PATCH v3 02/20] clk: tegra: periph: add new periph clks and muxes for Tegra210 Rhyland Klein
2015-05-01 18:53   ` Rhyland Klein [this message]
2015-05-01 18:54   ` [PATCH v3 14/20] clk: tegra: pll: Adjust vco_min if SDM present Rhyland Klein
2015-05-01 18:54   ` [PATCH v3 17/20] clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate Rhyland Klein
2015-05-01 18:54   ` [PATCH v3 18/20] clk: tegra: Add Super Gen5 Logic Rhyland Klein
2015-05-04 14:13   ` [PATCH v3 00/20] Tegra210 Clock Support Thierry Reding
     [not found]     ` <20150504141313.GA17642-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org>
2015-05-04 15:39       ` Rhyland Klein
2015-05-01 18:54 ` [PATCH v3 19/20] clk: tegra210: add support for Tegra210 clocks Rhyland Klein
2015-05-01 18:54 ` [PATCH v3 20/20] clk: tegra: pll: Fix issues with rates for VCO PLLs Rhyland Klein

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