From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
To: "jonathanh@nvidia.com" <jonathanh@nvidia.com>,
"mirza.krak@gmail.com" <mirza.krak@gmail.com>,
"swarren@wwwdotorg.org" <swarren@wwwdotorg.org>,
"thierry.reding@gmail.com" <thierry.reding@gmail.com>
Cc: "mark.rutland@arm.com" <mark.rutland@arm.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"pgaikwad@nvidia.com" <pgaikwad@nvidia.com>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"gnurou@gmail.com" <gnurou@gmail.com>,
"mturquette@baylibre.com" <mturquette@baylibre.com>,
"sboyd@codeaurora.org" <sboyd@codeaurora.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux@armlinux.org.uk" <linux@armlinux.org.uk>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
"pdeschrijver@nvidia.com" <pdeschrijver@nvidia.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: [Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table]
Date: Wed, 31 Aug 2016 07:15:45 +0000 [thread overview]
Message-ID: <1472627744.31008.2.camel@toradex.com> (raw)
In-Reply-To: 1472569308.5703.22.camel@toradex.com
On Wed, 2016-08-24 at 15:37 +0200, Mirza Krak wrote:
>
> From: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
> Add TEGRA20_CLK_NOR to init tabel and set default rate to 92 MHz
> which
> is max rate.
table
>
> Signed-off-by: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.g
> mane.org>
> ---
> Changes in v2:
> - no changes
>
> drivers/clk/tegra/clk-tegra20.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-
> tegra20.c
> index 837e5cb..13d3b5a 100644
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -1047,6 +1047,7 @@ static struct tegra_clk_init_table init_table[]
> __initdata = {
> { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },
> { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },
> { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },
> + { TEGRA20_CLK_NOR, TEGRA20_CLK_PLL_P, 92000000, 0 },
I'm just curious where that 92 MHz came from. According to the Tegra 2
Interface Design Guide up to 133 MHz should actually be possible.
>
> { TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 },
> { TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 },
> { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
> --
> 2.1.4
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next parent reply other threads:[~2016-08-31 7:15 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1472569308.5703.22.camel@toradex.com>
2016-08-31 7:15 ` Marcel Ziswiler [this message]
[not found] ` <1472627744.31008.2.camel-2KBjVHiyJgBBDgjK7y7TUQ@public.gmane.org>
2016-08-31 9:47 ` [Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table] Mirza Krak
2016-08-31 11:28 ` Marcel Ziswiler
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