From: Dmitry Osipenko <digetx@gmail.com>
To: Ben Dooks <ben.dooks@codethink.co.uk>
Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org, pdeschrijver@nvidia.com,
pgaikwad@nvidia.com, jonathanh@nvidia.co,
thierry.reding@gmail.com, linux-kernel@lists.codethink.co.uk
Subject: Re: [PATCH 6/8] clk: tegra30: add 2d and 3d idle clocks
Date: Tue, 24 Jul 2018 14:31:57 +0300 [thread overview]
Message-ID: <16130866.kpFhQUNOMP@dimapc> (raw)
In-Reply-To: <6750449.onR3KBHYkZ@dimapc>
On Monday, 23 July 2018 16:05:21 MSK Dmitry Osipenko wrote:
> On Friday, 20 July 2018 16:45:30 MSK Ben Dooks wrote:
> > The 2D and 3D clocks have an IDLE field in bits 15:8 so add these
> > clocks by making a 2D and 3D mux, and split the divider into the
> > standard 2D/3D ones and 2D/3D idle clocks.
> >
> > Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> > ---
> > drivers/clk/tegra/clk-id.h | 4 ++++
> > drivers/clk/tegra/clk-tegra-periph.c | 23 +++++++++++++++++++++--
> > drivers/clk/tegra/clk-tegra30.c | 8 ++++++++
> > include/dt-bindings/clock/tegra30-car.h | 7 ++++++-
> > 4 files changed, 39 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
> > index b616e33c5255..0d202a70ce66 100644
> > --- a/drivers/clk/tegra/clk-id.h
> > +++ b/drivers/clk/tegra/clk-id.h
> > @@ -91,8 +91,12 @@ enum clk_id {
> > tegra_clk_fuse_burn,
> > tegra_clk_gpu,
> > tegra_clk_gr2d,
> > + tegra_clk_gr2d_mux,
> > + tegra_clk_gr2d_idle,
> > tegra_clk_gr2d_8,
> > tegra_clk_gr3d,
> > + tegra_clk_gr3d_mux,
> > + tegra_clk_gr3d_idle,
> > tegra_clk_gr3d_8,
> > tegra_clk_hclk,
> > tegra_clk_hda,
> > diff --git a/drivers/clk/tegra/clk-tegra-periph.c
> > b/drivers/clk/tegra/clk-tegra-periph.c index 47e5b1ac1a69..83967dac93f2
> > 100644
> > --- a/drivers/clk/tegra/clk-tegra-periph.c
> > +++ b/drivers/clk/tegra/clk-tegra-periph.c
> > @@ -263,6 +263,21 @@
> > .flags = _flags, \
> > }
> >
> > +#define GATE_DIV(_name, _parent_name, _offset, \
> > + _div_shift, _div_width, _div_frac_width, _div_flags, \
> > + _clk_num, _gate_flags, _clk_id, _flags) \
> > + { \
> > + .name = _name, \
> > + .clk_id = _clk_id, \
> > + .offset = _offset, \
> > + .p.parent_name = _parent_name, \
> > + .periph = TEGRA_CLK_PERIPH(0, 0, 0, \
> > + _div_shift, _div_width, \
> > + _div_frac_width, _div_flags, \
> > + _clk_num, _gate_flags, NULL, NULL), \
> > + .flags = _flags \
> > + }
> > +
> > #define PLLP_BASE 0xa0
> > #define PLLP_MISC 0xac
> > #define PLLP_MISC1 0x680
> > @@ -646,8 +661,12 @@ static struct tegra_periph_init_data periph_clks[] = {
> > MUX("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0,
> tegra_clk_epp),
> > MUX("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0,
> > tegra_clk_host1x), MUX("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60,
> > 0, tegra_clk_mpe), - MUX("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D,
> 21,
> > 0, tegra_clk_gr2d), - MUX("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D,
> 24,
> > 0, tegra_clk_gr3d), + MUX("2d_mux", mux_pllm_pllc_pllp_plla,
> CLK_SOURCE_2D,
> > 0, TEGRA_PERIPH_NO_DIV | TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_NO_GATE,
> > tegra_clk_gr2d_mux), + GATE_DIV("2d", "2d_mux", CLK_SOURCE_2D, 0, 8, 1,
> > TEGRA_DIVIDER_ROUND_UP,21, 0, tegra_clk_gr2d, 0), + GATE_DIV("2d_idle",
> > "2d_mux", CLK_SOURCE_2D, 8, 8, 1, TEGRA_DIVIDER_ROUND_UP, 0,
> > TEGRA_PERIPH_NO_GATE | TEGRA_PERIPH_NO_RESET, tegra_clk_gr2d_idle, 0),
> > + MUX("3d_mux", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 0,
>
> Now that the actual parent clock is specified by the "mux" clock, you have to
> adjust the tegra_clk_init_table accordingly.
>
>
>
>
The 3d/2d clocks do not have a parent on T20 with these patches being applied.
# cat /sys/kernel/debug/clk/clk_summary
enable prepare protect duty
clock count count count rate accuracy phase cycle
---------------------------------------------------------------------------------------------
clock 0 0 0 32768 0 0 50000
3d 1 1 0 0 0 0 50000
2d 1 1 0 0 0 0 50000
clk_32k 2 2 0 32768 0 0 50000
blink_override 1 1 0 32768 0 0 50000
blink 2 2 0 32768 0 0 50000
kbc 0 0 0 32768 0 0 50000
rtc 2 2 0 32768 0 0 50000
...
Same on T30.
# cat /sys/kernel/debug/clk/clk_summary
enable prepare protect duty
clock count count count rate accuracy phase cycle
---------------------------------------------------------------------------------------------
...
3d_idle 0 0 0 0 0 0 50000
3d 1 1 0 0 0 0 50000
2d_idle 0 0 0 0 0 0 50000
2d 1 1 0 0 0 0 50000
clk_32k 2 2 0 32768 0 0 50000
blink_override 1 1 0 32768 0 0 50000
...
next prev parent reply other threads:[~2018-07-24 11:31 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-20 13:45 tegra clock updates and fixes Ben Dooks
2018-07-20 13:45 ` [PATCH 1/8] clk: tegra: implement reset status callback Ben Dooks
2018-07-20 13:45 ` [PATCH 2/8] clk: tegra: host1x has fractional divider Ben Dooks
2018-07-23 8:50 ` Peter De Schrijver
2018-07-23 9:32 ` Ben Dooks
2018-07-23 11:12 ` Peter De Schrijver
2018-07-23 11:32 ` Ben Dooks
2018-07-20 13:45 ` [PATCH 3/8] clk: tegra: fix fractional clocks for VDI, VI, EPP, MPE, 2D and 3D Ben Dooks
2018-07-23 8:50 ` Peter De Schrijver
2018-07-20 13:45 ` [PATCH 4/8] clk: tegra: fix MUX_I2S_SPDIF macro Ben Dooks
2018-07-20 13:45 ` [PATCH 5/8] clk: tegra: add mux-only clock option Ben Dooks
2018-07-20 13:45 ` [PATCH 6/8] clk: tegra30: add 2d and 3d idle clocks Ben Dooks
2018-07-22 11:55 ` Dmitry Osipenko
2018-07-23 8:28 ` Ben Dooks
2018-07-23 11:33 ` Dmitry Osipenko
2018-07-23 11:37 ` Ben Dooks
2018-07-23 13:05 ` Dmitry Osipenko
2018-07-24 11:31 ` Dmitry Osipenko [this message]
2018-07-24 12:32 ` Ben Dooks
2018-07-20 13:45 ` [PATCH 7/8] clk: tegra: replace warn on with single line Ben Dooks
2018-07-20 13:45 ` [PATCH 8/8] clk: tegra: show clock name in error from _calc_rate Ben Dooks
2018-07-26 13:32 ` tegra clock updates and fixes Ben Dooks
2018-07-26 15:22 ` Stephen Boyd
2018-07-27 8:22 ` Ben Dooks
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=16130866.kpFhQUNOMP@dimapc \
--to=digetx@gmail.com \
--cc=ben.dooks@codethink.co.uk \
--cc=jonathanh@nvidia.co \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@lists.codethink.co.uk \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=pdeschrijver@nvidia.com \
--cc=pgaikwad@nvidia.com \
--cc=thierry.reding@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).