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Svyatoslav Ryhel Cc: Thierry Reding , Thierry Reding , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Dmitry Osipenko , Charan Pedumuru , linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: Re: [PATCH v1 01/19] clk: tegra: init CSUS clock for Tegra20 and Tegra30 Date: Thu, 28 Aug 2025 17:13:22 +0900 Message-ID: <1797126.QkHrqEjB74@senjougahara> In-Reply-To: References: <20250819121631.84280-1-clamor95@gmail.com> <14287352.RDIVbhacDa@senjougahara> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-ClientProxiedBy: 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IA1PR12MB6604 On Wednesday, August 27, 2025 7:45=E2=80=AFPM Svyatoslav Ryhel wrote: > =D1=81=D1=80, 27 =D1=81=D0=B5=D1=80=D0=BF. 2025=E2=80=AF=D1=80. =D0=BE 13= :36 Mikko Perttunen =D0=BF=D0=B8=D1=88=D0=B5: > > On Wednesday, August 27, 2025 1:32=E2=80=AFPM Svyatoslav wrote: > > > 27 =D1=81=D0=B5=D1=80=D0=BF=D0=BD=D1=8F 2025=E2=80=AF=D1=80. 07:09:45= GMT+03:00, Mikko Perttunen > >=20 > > =D0=BF=D0=B8=D1=88=D0=B5: > > > >On Tuesday, August 19, 2025 9:16=E2=80=AFPM Svyatoslav Ryhel wrote: > > > >> CSUS clock is required to be enabled on camera device configuratio= n > > > >> or > > > >> else camera module refuses to initiate properly. > > > >>=20 > > > >> Signed-off-by: Svyatoslav Ryhel > > > >> --- > > > >>=20 > > > >> drivers/clk/tegra/clk-tegra20.c | 1 + > > > >> drivers/clk/tegra/clk-tegra30.c | 1 + > > > >> 2 files changed, 2 insertions(+) > > > >>=20 > > > >> diff --git a/drivers/clk/tegra/clk-tegra20.c > > > >> b/drivers/clk/tegra/clk-tegra20.c index 551ef0cf0c9a..42f8150c6110 > > > >> 100644 > > > >> --- a/drivers/clk/tegra/clk-tegra20.c > > > >> +++ b/drivers/clk/tegra/clk-tegra20.c > > > >> @@ -1043,6 +1043,7 @@ static struct tegra_clk_init_table init_tabl= e[] > > > >> =3D { > > > >>=20 > > > >> { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, > > > >> { TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 }, > > > >> { TEGRA20_CLK_PWM, TEGRA20_CLK_PLL_P, 48000000, 0 }, > > > >>=20 > > > >> + { TEGRA20_CLK_CSUS, TEGRA20_CLK_CLK_MAX, 6000000, 1 }, > > > >>=20 > > > >> /* must be the last entry */ > > > >> { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 }, > > > >> =20 > > > >> }; > > > >>=20 > > > >> diff --git a/drivers/clk/tegra/clk-tegra30.c > > > >> b/drivers/clk/tegra/clk-tegra30.c index 82a8cb9545eb..70e85e2949e0 > > > >> 100644 > > > >> --- a/drivers/clk/tegra/clk-tegra30.c > > > >> +++ b/drivers/clk/tegra/clk-tegra30.c > > > >> @@ -1237,6 +1237,7 @@ static struct tegra_clk_init_table init_tabl= e[] > > > >> =3D { > > > >>=20 > > > >> { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 }, > > > >> { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 }, > > > >> { TEGRA30_CLK_PWM, TEGRA30_CLK_PLL_P, 48000000, 0 }, > > > >>=20 > > > >> + { TEGRA30_CLK_CSUS, TEGRA30_CLK_CLK_MAX, 6000000, 1 }, > > > >>=20 > > > >> /* must be the last entry */ > > > >> { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, > > > >> =20 > > > >> }; > > > > > > > >I looked into what this clock does and it seems to be a gate for the > > > >CSUS > > > >pin, which provides an output clock for camera sensors (VI MCLK). > > > >Default > > > >source seems to be PLLC_OUT1. It would be good to note that on the > > > >commit > > > >message, as I can't find any documentation about the CSUS clock > > > >elsewhere. > > > > > > > >What is the 6MHz rate based on? > > >=20 > > > 6mhz is the statistic value which I was not able to alter while testi= ng. > > > I > > > have tried 12mhz and 24mhz too but it remained 6mhz, so I left it 6mh= z. > > >=20 > > > >Since this seems to be a clock consumed by the sensor, it seems to m= e > > > >that > > > >rather than making it always on, we could point to it in the sensor'= s > > > >device tree entry. > > >=20 > > > Sensor device tree uses vi_sensor as clocks source and sensor drivers > > > don't > > > support multiple linked clocks. > >=20 > > AIUI vi_sensor is an internal clock so the sensor cannot be receiving i= t > > directly. Perhaps the sensor is actually connected to csus, and the rea= son > > we need to enable it is to allow the vi_sensor clock to pass through th= e > > csus gate? > >=20 > > That leaves the question of why the csus pad would be muxed to vi_senso= r > > by > > default, but perhaps there's an explanation for that. >=20 > From downstream T30 sources csus and vi_sensor are always called in > pair (6MHz csus and 24MHz for vi_sensor), naturally I assumed that > latter is used as camera reference clock since most sensors has > reference clock around 24 MHz It's possible that the csus pad is still outputting 24MHz. The pinmux optio= ns=20 for the csus pad are various clocks, so it would seem logical that the cloc= k=20 source for the pad is one of those clocks. However, on the clock framework= =20 side, the csus clock is just a gate. What I'm confused about is that since = on=20 the clock framework side the parent of csus is currently set to clk_m, I do= n't=20 know why setting the rate of csus would affect the output of the pad, given= =20 clk_m is not one of the options for the pinmux. It's be good to verify the register value for the csus pinmux to see where = it=20 thinks the clock is coming from, and then check how that matches with what = we=20 are seeing. >=20 > > > >Cheers, > > > >Mikko