From: Mark Brown <broonie-yzvPICuk2AATkU/dhu1WVueM+bqZidxxQQ4Iyu8u01E@public.gmane.org>
To: Colin Cross <ccross-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>
Cc: Marc Dietrich <marvin24-Mmb7MZpHnFY@public.gmane.org>,
"linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org>,
Allen Martin <amartin-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Subject: Re: cpu clock change latency
Date: Tue, 27 Sep 2011 16:30:22 +0100 [thread overview]
Message-ID: <20110927153021.GA16150@sirena.org.uk> (raw)
In-Reply-To: <CAMbhsRTiqLZ2bSefh-DnmDY0RB4JGkSmumh8Tt_7217BsHsa7Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Fri, Sep 23, 2011 at 09:49:53AM -0700, Colin Cross wrote:
> cpu-tegra.c says latency is 300 uS because relocking the CPU pll has a
> udelay(300). 400 nS would just make the ondemand governor sample more
> often than it means to. I doubt changing it to 400 uS makes any
> difference.
The interactive effect of a higher transition latency with ondemand can
be rather visible.
It's probably also worth mentioning that if there's regulators used for
voltage scaling the system really ought to be including latency for them
in the estimate, for voltage increases the regulator needs to be updated
prior to the SoC side starting off.
next prev parent reply other threads:[~2011-09-27 15:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-23 14:39 cpu clock change latency Marc Dietrich
[not found] ` <201109231639.33651.marvin24-Mmb7MZpHnFY@public.gmane.org>
2011-09-23 16:44 ` Allen Martin
2011-09-23 16:49 ` Colin Cross
[not found] ` <CAMbhsRTiqLZ2bSefh-DnmDY0RB4JGkSmumh8Tt_7217BsHsa7Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2011-09-27 15:30 ` Mark Brown [this message]
[not found] ` <20110927153021.GA16150-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2011-09-27 19:31 ` Marc Dietrich
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