Re: cpu clock change latency

[Marc Dietrich <marvin24-Mmb7MZpHnFY@public.gmane.org>]

On Tuesday 27 September 2011 17:30:22 Mark Brown wrote:
> On Fri, Sep 23, 2011 at 09:49:53AM -0700, Colin Cross wrote:
> > cpu-tegra.c says latency is 300 uS because relocking the CPU pll has a
> > udelay(300).  400 nS would just make the ondemand governor sample more
> > often than it means to.  I doubt changing it to 400 uS makes any
> > difference.
> 
> The interactive effect of a higher transition latency with ondemand can
> be rather visible.

True, given the 400 µs latency and the multiplier of 1000 we end up having 
a sample_rate of the ondemand scheduler of 0.4 seconds, which is very 
"feelable". My AMD desktop announces a 1 µs latency so the default sampling 
rate is only 10 ms. 

A transition latency of 400 ns will set the sampling_rate to 10 ms (the 
minimum value allowed, so 10 µs would have the same effect). 

So doing an "echo 40000 > 
/sys/devices/system/cpu/cpufreq/ondemand/sampling_rate" is the best we can 
do now and almost produces the same result as 10000. 

We additionaly found that setting io_is_busy=1 improves the transfer rate 
of the mmc by 50%. 

> It's probably also worth mentioning that if there's regulators used for
> voltage scaling the system really ought to be including latency for them
> in the estimate, for voltage increases the regulator needs to be updated
> prior to the SoC side starting off.

which would make things even worse :-(

Marc