From mboxrd@z Thu Jan 1 00:00:00 1970 From: Olof Johansson Subject: Re: [PATCH 03/11] gpio: tegra: fix register address calculations for Tegra30 Date: Wed, 4 Apr 2012 10:57:22 -0700 Message-ID: <20120404175722.GC29919@quad.lixom.net> References: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org> <1333148404-17691-4-git-send-email-swarren@wwwdotorg.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1333148404-17691-4-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Stephen Warren Cc: Colin Cross , Linus Walleij , linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Stephen Warren List-Id: linux-tegra@vger.kernel.org On Fri, Mar 30, 2012 at 04:59:56PM -0600, Stephen Warren wrote: > From: Stephen Warren > > Tegra20 and Tegra30 share the same register layout within registers, but > the addresses of the registers is a little different. Fix the driver to > cope with this. > > @@ -333,6 +336,26 @@ static struct irq_chip tegra_gpio_irq_chip = { > #endif > }; > > +struct tegra_gpio_soc_config { > + u32 bank_stride; > + u32 upper_offset; > +}; > + > +static struct tegra_gpio_soc_config tegra20_gpio_config = { > + .bank_stride = 0x80, > + .upper_offset = 0x800, > +}; > + > +static struct tegra_gpio_soc_config tegra30_gpio_config = { > + .bank_stride = 0x100, > + .upper_offset = 0x80, > +}; Hmm. I wonder if this would be better to just describe in the device tree bindings for the gpio controller? Perhaps split the reg property in a higher and lower to take care of the offset, and add a nvidia,bank-stride= property? -Olof