Re: Multi-platform, and secure-only ARM errata workarounds

[Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]

On Mon, Mar 04, 2013 at 07:34:36AM +0100, Peter De Schrijver wrote:
> On Fri, Mar 01, 2013 at 06:37:27PM +0100, Stephen Warren wrote:
> 
> ...
> 
> > Since some of the bits that enable WARs are banked per CPU, the WAR
> > needs to be enabled by code running on each individual CPU, each time
> > it's powered on. When a secure monitor exists, the CPU will boot through
> > it (at least on Tegra, there is a single register that defines the boot
> > vector for all CPUs; I don't know if that fact is ARM-architectural or
> > not), so the secure monitor can apply the WAR if needed. However, when
> > there is no secure monitor and the kernel runs in secure world, the
> > kernel would have to apply those WARs, since the only code that runs is
> > in the kernel.
> > 
> 
> The boot vector register is Tegra specific. At least on OMAP all cores boot
> from ROM afaik.

Nicolas Pitre suggested a slightly different solution to me:

1) Handle CPU0 errata WARs in the bootloader
2) Indicate in device tree if linux is booting in secude mode or non-secure
   mode.
3) Use this information in the kernel to decide how to apply the WARs for
   secondary core bringup and after powerungating.

Cheers,

Peter.