Re: [PATCH] clk: tegra: Allow PLLE training to succeed

[Thierry Reding <thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>]

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On Fri, Mar 22, 2013 at 01:48:22PM -0700, Mike Turquette wrote:
> Quoting Stephen Warren (2013-03-15 12:28:21)
> > On 03/14/2013 09:27 AM, Thierry Reding wrote:
> > > Under some circumstances the PLLE needs to be retrained, in which case
> > > access to the PMC registers is required. Fix this by passing a pointer
> > > to the PMC registers instead of NULL when registering the PLLE clock.
> > 
> > Mike, I believe this patch is appropriate as a fix for v3.9. I assume
> > you'll take it through the clock tree? Thanks.
> 
> Does this patch fix a crash or a documented failure?  Linus is being
> more strict about taking fixes in the -rc cycles these days and knowing
> exactly what behavior this fixes would be beneficial.

This fixes a failure where the clock can't be retrained. Under some
circumstances the timing is such that retraining isn't required, in
which case the code runs normally. However I've seen in happen that
the PLL isn't stable in other cases, so the code tries to retrain.

But the current code doesn't allow retraining to happen because the
MC registers aren't accessible for the PLLE and therefore the
clk_plle_training() function immediately errors out with -ENOSYS.

Comparing to Tegra30 this is obviously just a typo when registering
the PLLE clock and the virtual address to the PMC registers can be
passed in at PLLE registration time to resolve this issue.

Thierry

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